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alc5672 multi-channel audio hub/codec with gen. 3 voice dsp and sounzreal tm post-processing for mobile devices datasheet rev. 0.74 11 july 2013 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3- 578 -0211. fax: +886-3- 577 -6047 www.realtek.com
alc5672 datasheet ii rev. 0.75 copyright ?2013 realtek semiconductor corp. all rights reserved. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document as is, without warranty of any kind. realtek may make improvements and/or changes in this document or in the product described in this document at any time. this document could include technical inaccuracies or typographical errors. trademarks realtek is a trademark of realtek semiconductor corporation. other names mentioned in this document are trademarks/registered trademarks of their respective owners. using this document this document is intended for the hardware and software engineers general information on the realte k alc5672 audio codec ic. though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.
alc5672 datasheet iii rev. 0.75 revision history revision release date summary 0.4 201 2/ 12 /28 first full version release 0.5 201 3/1/28 modify register typos modify order information 0.6 2013/3/4 modify clock rate supporting for tdm interface modify application circuit 0.7 2013/3/21 modify typos modify application circuit 0.71 2013/4/15 modify in2p pin share function 0.72 2013/ 5/29 add function description 0.73 2013/6/6 update application circuit 0.74 2013/7/11 add jd1 function description update application circuit
alc5672 datasheet iv rev. 0.75 table of contents 1. general description ........................................................................................ 1 2. features ................................................................................................................... 2 3. power/ground operation conditions .................................................. 4 4. system application ........................................................................................... 4 5. function block and mixer path ............................................................... 5 5.1. f unction b lock ........................................................................................................................... 5 5.2. a udio m ixer p at h ....................................................................................................................... 6 5.3. d igital m ixer p ath ..................................................................................................................... 7 6. pin assignments ................................................................................................... 8 7. pin descriptions .................................................................................................. 9 7.1. d igital i/o p ins ............................................................................................................................ 9 7.2. a nalog i/o p ins ......................................................................................................................... 10 7.3. f i lter /r eference ...................................................................................................................... 11 7.4. p ower /g round ........................................................................................................................... 11 8. function description .................................................................................... 12 8.1. s ystem c onnection ............................................................................................. 12 8.2. p ower .................................................................................................................... 13 8.3. p ower s upply o n /o ff s equence ........................................................................ 14 8.4. r eset ..................................................................................................................... 16 8.4.1. power-on reset (por) ................................................................................... 16 8.4.2. software reset ................................................................................................ . 16 8.5. c locking ............................................................................................................... 17 8.5.1. phase-locked loop ......................................................................................... 18 8.5.2. i 2 c and two i 2 s/pcm interface ..................................................................... 19 8.6. d igital d ata i nterface ..................................................................................... 22 8.6.1. two i 2 s/pcm interface ................................................................................... 22 8.7. a udio d ata p ath ................................................................................................ . 26 8.7.1. 2 analog adcs with 6-channel record path ................................................ 26 8.7.2. 4 dacs with 4-channel playback path ......................................................... 27 8.7.3. mixers ............................................................................................................. 28 8.8. a nalog a udio i nput p ort .................................................................................. 29 8.9. a nalog a udio o utput p ort ............................................................................... 30
alc5672 datasheet v rev. 0.75 8.10. m ulti -f unction p ins ........................................................................................... 31 8.11. drc and agc f unction ..................................................................................... 34 8.12. s ounz r eal tm p ost -p rocessing .......................................................................... 40 8.13. e qualizer b lock ................................................................................................ . 40 8.14. w ind n oise r eduction f ilter ............................................................................ 40 8.15. i 2 c c ontrol i nterface ....................................................................................... 43 8.15.1. address setting ............................................................................................... 43 8.15.2. complete data transfer ................................................................................. 43 8.16. gpio, i nterrupt and j ack d etection ............................................................... 45 8.17. p ush b utton d etection ...................................................................................... 48 8.18. p ower m anagement ............................................................................................ 50 8.19. g en .3 v oice dsp f unction ................................................................................. 51 8.20. m ulti -j ack j ack d etection p in (jd1) ............................................................... 53 9. registers list ..................................................................................................... 54 9.1. r egister m ap ....................................................................................................... 54 9.2. mx - 00 h : s/w r eset & d evice id ....................................................................... 58 9.3. mx - 02 h : h eadphone o utput c ontrol ............................................................. 58 9.4. mx - 03 h : line o utput c ontrol ........................................................................ 59 9.5. mx - 0a h : in1 p ort c ontrol - 1 .......................................................................... 61 9.6. mx - 0b h : in1 p ort c ontrol - 2 .......................................................................... 61 9.7. mx - 0c h : in1 p ort c ontrol - 3 .......................................................................... 62 9.8. mx - 0e h : in2 i nput c ontrol .............................................................................. 62 9.9. mx - 0f h : inl & inr v olume c ontrol .............................................................. 63 9.10. mx- 19 h : dacl1/r1 d igital v olume ............................................................... 64 9.11. mx - 1a h : dacl2/r2 d igital v olume ............................................................... 64 9.12. mx - 1b h : dacl2/r2 m ute /u n -m ute c ontrol ................................................ 66 9.13. mx - 1c h : s tereo 1 adc d igital v olume c ontrol .......................................... 67 9.14. mx - 1d h : m ono adc d igital v olume c ontrol ............................................. 68 9.15. mx - 1e h : adc d igital b oost g ain c ontrol ................................................... 69 9.16. mx - 1f h : s tereo 2 adc d igital v olume c ontrol .......................................... 70 9.17. mx - 20 h : m ono adc d igital b oost g ain c ontrol ........................................ 71 9.18. mx - 26 h : s tereo 2 adc d igital m ixer c ontrol ............................................. 71 9.19. mx - 27 h : s tereo 1 adc d igital m ixer c ontrol ............................................. 72 9.20. mx - 28 h : m ono adc d igital m ixer c ontrol ................................................. 73 9.21. mx - 29 h : s tereo adc to dac d igital m ixer c ont rol ................................ . 74 9.22. mx - 2a h : s tereo dac d igital m ixer c ontrol ............................................... 74 9.23. mx - 2b h : m ono dac d igital m ixer c ontrol ................................................. 75 9.24. mx - 2c h : dac d igital m ixer c ontrol ............................................................ 76 9.25. mx - 2d h : v oice dsp p ath c ontrol 1 ............................................................... 77
alc5672 datasheet vi rev. 0.75 9. 26. mx - 2e h : v oice dsp v olume c ontrol ............................................................. 78 9.27. mx - 2f h : i nterface dac/adc d ata c ontrol ................................................ 79 9.28. mx - 31 h : s peaker c ontrol 1 .............................................................................. 79 9.29. mx - 3b h : recmixl c ontrol 1 .......................................................................... 80 9.30. mx - 3c h : recmixl c ontrol 2 .......................................................................... 80 9.31. mx - 3d h : recmixr c ontrol 1 ......................................................................... 81 9.32. mx - 3e h : recmixr c ontrol 2 .......................................................................... 81 9.33. mx - 45 h : hpomix c ontrol ............................................................................... 82 9.34. mx - 4f h : outmixl c ontrol ............................................................................ 82 9.35. mx - 52 h : outmixr c ontrol ............................................................................ 83 9.36. mx - 53 h : loutmix c ontrol ............................................................................. 83 9.37. mx - 61 h : p ower m anagement c ontrol 1 ........................................................ 84 9.38. mx - 62 h : p ower m anagement c ontrol 2 ........................................................ 85 9.39. mx - 63 h : p ower m anagement c ontrol 3 ........................................................ 85 9.40. mx - 64 h : p ower m anagement c ontrol 4 ........................................................ 86 9.41. mx - 65 h : p ower m anagement c ontrol 5 ........................................................ 87 9.42. mx - 66 h : p ower m anagement c ontrol 6 ........................................................ 88 9.43. mx - 6a h : p rivate r egister i ndex ..................................................................... 88 9.44. mx - 6c h : p rivate r egister d ata ...................................................................... 88 9.45. mx - 70 h : i2s1 d igital i nterface c ontrol ....................................................... 89 9.46. mx - 71 h : i2s2 d igital i nterface c ontrol ....................................................... 89 9.47. mx - 73 h : adc/dac c lock c ontrol ................................................................ . 90 9.48. mx - 74 h : adc/dac hp f c ontrol ..................................................................... 91 9.49. mx - 75 h : d igital m icrophone c ontrol 1 ........................................................ 92 9.50. mx - 76 h : d igital m icrophone c ontrol 2 ........................................................ 93 9.51. mx - 77 h : tdm i nterface c ontrol 1 ................................................................ . 94 9.52. mx - 78 h : tdm i nterface c ontrol 2 ................................................................ . 95 9.53. mx - 79 h : tdm i nterface c ontrol 3 ................................................................ . 96 9.54. mx - 7f h : c lock c ontrol 1 ................................................................................. 97 9.55. mx - 80 h : g lobal c lock c ontrol ...................................................................... 97 9.56. mx - 81 h : pll c ontrol 1 ..................................................................................... 98 9.57. mx - 82 h : pll c ontrol 2 ..................................................................................... 98 9.58. mx - 83 h : asrc c ontrol 1 .................................................................................. 99 9.59. mx - 84 h : asrc c ontrol 2 ................................................................................ 100 9.60. mx - 85 h : asrc c ontrol 3 ................................................................................ 101 9.61. mx - 8a h : asrc c ontrol 4 ............................................................................... 102 9.62. mx - 8c h : asrc c ontrol 5 ............................................................................... 102 9.63. mx - 8e h : hp a mp c ontrol 1 ............................................................................. 103 9.64. mx - 8f h : hp a mp c ontrol 2 ............................................................................. 103
alc5672 datasheet vii rev. 0.75 9.65. mx - 93 h : micbias c ontrol ............................................................................ 104 9.66. mx - 94 h : jd1 c ontrol ....................................................................................... 104 9.67. mx - ae h : adc p ath eq c ontrol 1 ................................................................ . 105 9.68. mx - af h : adc p ath eq c ontrol 2 ................................................................ . 106 9.69. mx - b0 h : dac p ath eq c ontrol 1 .................................................................. 107 9.70. mx - b1 h : eq c ontrol 2 .................................................................................... 108 9.71. mx - b2 h : drc c ont rol 1 ................................................................................. 109 9.72. mx - b3 h : drc c ontrol 2 ................................................................................. 109 9.73. mx - b4 h : drc c ontrol 3 ................................................................................. 110 9.74. mx - b5 h : drc c ontrol 4 ................................................................................. 111 9.75. mx - b6 h : drc c ontrol 5 ................................................................................. 112 9.76. mx - b7 h : drc c ontrol 6 ................................................................................. 113 9.77. mx - bb h : j ack d etection c ontrol 1 .............................................................. 113 9.78. mx - bd h : irq c ontrol 1 .................................................................................. 114 9.79. mx - be h : irq c ontrol 2 .................................................................................. 115 9.80. mx - bf h : irq c ontrol 3 ................................................................................... 116 9.81. mx - c0 h : gpio c ontrol 1 ................................................................................ 116 9.82. mx - c1 h : gpio c ontrol 2 ................................................................................ 117 9.83. mx - c2 h : gpio c ontrol 3 ................................................................................ 118 9.84. mx - cf h : s ounz r eal tm b ass b ack c ontr ol .................................................. 119 9.85. mx - d0 h : s ounz r eal tm t ru t reble c ontrol 1 .............................................. 11 9 9.86. mx - d1 h : s ounz r eal tm t ru t reble c ontrol 2 .............................................. 120 9.87. mx - d3 h : s tereo 1 adc w ind f ilter c ontrol 1 ............................................ 120 9.88. mx - d4 h : s tereo 1 adc w ind f ilter c ontrol 2 ............................................ 121 9.89. mx - d9 h : s oft v olume & zcd c ontrol 1 ...................................................... 122 9.90. mx - da h : s oft v olume & zcd c ontrol 2 ..................................................... 123 9.91. mx - db h : i nl ine c ommand c ontrol 1 ............................................................ 123 9.92. mx - dc h : i nline c ommand c ontrol 2 ............................................................ 124 9.93. mx - dd h : i nline c ommand c ontrol 3 ............................................................ 125 9.94. mx - e0 h : v oice dsp c ontrol 1 ....................................................................... 125 9.95. mx - e1 h : v oice dsp c ontrol 2 ....................................................................... 126 9.96. mx - e2 h : v oice dsp c ontrol 3 ....................................................................... 126 9.97. mx - e3 h : v oice dsp c ontrol 4 ....................................................................... 126 9.98. mx - e4 h : v oice dsp c ontrol 5 ....................................................................... 127 9.99. mx - e5 h : v oice dsp c ontrol 6 ....................................................................... 127 9.100. mx - ec h : m ono adc w ind f ilter c ontrol 1 ............................................ 127 9.101. mx - ed h : m ono adc w ind f ilter c ontrol 2 ............................................ 128 9.102. mx - ee h : s tereo 2 adc w ind f ilter c ontrol 1 ........................................ 128 9.103. mx - ef h : s ter eo 2 adc w ind f ilter c ontrol 2 ........................................ 130
alc5672 datasheet viii rev. 0.75 9.104. mx - f8 h : j ack d etection c ontrol .............................................................. 130 9.105. mx - f9 h : j ack d etection c ontrol .............................................................. 131 9.106. mx - fa h : g eneral c ontrol 1 ...................................................................... 131 9.107. mx - fb h : g eneral c ontrol 2 ....................................................................... 132 9.108. pr - 3d h : adc/dac reset c ontrol ........................................................... 132 9.109. pr - a4 h : dac_l eq (lpf: a 1) ........................................................................ 133 9.110. pr - a5 h : dac_l eq (lpf:h0) ....................................................................... 133 9.111. pr - a6 h : dac_r eq (lpf: a 1) ....................................................................... 133 9.112. pr - a7 h : dac_r eq (lpf:h0) ....................................................................... 134 9.1 13. pr - ae h : dac_l eq (bpf2: a 1) ..................................................................... 134 9.114. pr - af h : dac_l eq (bpf2: a 2) ..................................................................... 134 9.115. pr - b0 h : dac_l eq (bpf2:h0) ..................................................................... 134 9.116. pr - b1 h : dac_r eq (bpf2: a 1) ..................................................................... 135 9.117. pr - b2 h : dac_r eq (bpf2: a 2) ..................................................................... 135 9.118. pr - b3 h : dac_r eq (bpf2:h0) ..................................................................... 135 9.119. pr - b4 h : dac_l eq (bpf3: a 1) ...................................................................... 135 9.120. pr - b5 h : dac_l eq (bpf3: a 2) ...................................................................... 136 9.121. pr - b6 h : dac_l eq (bpf3:h0) ..................................................................... 136 9.122. pr - b7 h : dac_r eq (bpf3: a 1) ..................................................................... 136 9.123. pr - b8 h : dac_r eq (bpf3: a 2) ..................................................................... 136 9.124. pr - b9 h : dac_r eq (bpf3:h0) ..................................................................... 137 9.125. pr - ba h : dac_l eq (bpf4: a 1) ..................................................................... 137 9.126. pr - bb h : dac_l eq (bpf4: a 2) ..................................................................... 137 9.127. pr - bc h : dac_l eq (bpf4:h0) .................................................................... 137 9.128. pr - bd h : dac_r eq (bpf4: a 1) ..................................................................... 138 9.129. pr - be h : dac_r eq (bpf4: a 2) ..................................................................... 138 9.130. pr - bf h : dac_r eq (bpf4:h0) ..................................................................... 138 9.131. pr - c0 h : dac_l eq (hpf1: a 1) ..................................................................... 138 9.132. pr - c1 h : dac_l eq (hpf1:h0) ..................................................................... 139 9.133. pr -c2 h : dac_r eq (hpf1: a 1) ..................................................................... 139 9.134. pr - c3 h : dac_r eq (hpf1:h0) ..................................................................... 139 9.135. pr - c4 h : dac_l eq (hpf2: a 1) ..................................................................... 139 9.136. pr - c5 h : dac_l eq (hpf2: a 2) ..................................................................... 140 9.137. pr - c6 h : dac_l eq (hpf2:h0) ..................................................................... 140 9.138. pr - c7 h : dac_r eq (hpf2: a 1) ..................................................................... 140 9.139. pr - c8 h : dac_r eq (hpf2: a 2) ..................................................................... 140 9.140. pr - c9 h : dac_r eq (hpf2:h0) ..................................................................... 141 9.141. pr - ca h : dac_l eq p re -v olume c ontrol ................................................ 141 9.142. pr - cb h : dac_r eq p re -v olume c ontrol ................................................ 141
alc5672 datasheet ix rev. 0.75 9.143. pr - cc h : dac_l eq p ost -v olume c ontrol .............................................. 142 9.144. pr - cd h : dac_r eq p ost -v olume c ontrol .............................................. 142 9.145. pr - ce h : adc eq (lpf: a 1) ............................................................................ 142 9.146. pr - cf h : adc eq (lpf:h0) ............................................................................ 143 9.147. pr - d0 h : adc eq (bpf1: a 1) .......................................................................... 143 9.148. pr - d1 h : adc eq (bpf1: a 2) .......................................................................... 143 9.149. pr - d2 h : adc eq (bpf1:h0) ......................................................................... 143 9.150. pr - d3 h : adc eq (bpf2: a 1) .......................................................................... 144 9.151. pr - d4 h : adc eq (bpf2: a 2) .......................................................................... 144 9.152. pr - d5 h : adc eq (bpf2:h0) ......................................................................... 144 9.153. pr - d6 h : adc eq (bpf3: a 1) .......................................................................... 144 9.154. pr - d7 h : adc eq (bpf3: a 2) .......................................................................... 145 9.155. pr - d8 h : adc eq (bpf3:h0) ......................................................................... 145 9.156. pr - d9 h : adc eq (bpf4: a 1) .......................................................................... 145 9.157. pr - da h : adc eq (bpf4: a 2) ......................................................................... 145 9.158. pr -db h : adc eq (bpf4:h0) ......................................................................... 146 9.159. pr - dc h : adc eq (hpf1: a 1) ......................................................................... 146 9.160. pr - dd h : adc eq (hpf1:h0) ........................................................................ 146 9.161. pr - e1 h : adc eq p re -v olume c ontrol ...................................................... 146 9.162. pr - e2 h : adc eq p ost -v olume c ontrol .................................................... 147 9.16 3. pr - e5 h : dac_l b iquad eq (bpf1: h 0- 1) ..................................................... 147 9.164. pr - e6 h : dac_l b iquad eq (bpf1: h 0- 2) ..................................................... 147 9.165. pr - e7 h : dac_l b iquad eq (bpf1: b 1- 1) ..................................................... 147 9.166. pr - e8 h : dac_l b iquad eq (bpf1: b 1- 2) ..................................................... 148 9.167. pr - e9 h : dac_l b iquad eq (bpf1: b 2- 1) ..................................................... 148 9.168. pr - ea h : dac_l b iquad eq (bpf1: b 2- 2) .................................................... 148 9.169. pr - eb h : dac_l b iquad eq (bpf1: a 1- 1) .................................................... 148 9.170. pr - ec h : dac_l b iquad eq (bpf1: a 1- 2) .................................................... 149 9.171. pr - ed h : dac_l b iquad eq (bpf1: a 2- 1) .................................................... 149 9.172. pr - ee h : dac_l b iquad eq (bpf1: a 2- 2) .................................................... 149 9.173. pr - ef h : dac_r b iquad eq (bpf1: h 0- 1) .................................................... 149 9.174. pr - f0 h : dac_r b iquad eq (bpf1: h 0- 2) ..................................................... 150 9.175. pr - f1 h : dac_r b iquad eq (bpf1: b 1- 1) ..................................................... 150 9.176. pr - f2 h : dac_r b iquad eq (bpf1: b 1- 2) ..................................................... 150 9.177. pr - f3 h : dac_r b iquad eq (bpf1: b 2- 1) ..................................................... 150 9.178. pr - f4 h : dac_r b iquad eq (bpf1: b 2- 2) ..................................................... 151 9.179. pr - f5 h : dac_r b iquad eq (bpf1: a 1- 1) ..................................................... 151 9.180. pr - f6 h : dac_r b iquad eq (bpf1: a 1- 2) ..................................................... 151 9.181. pr - f7 h : dac_r b iquad eq (bpf1: a 2- 1) ..................................................... 151
alc5672 datasheet x rev. 0.75 9.182. pr - f8 h : dac_r b iquad eq (bpf1: a 2- 2) ..................................................... 152 9.183. mx - fe h : v endor id ....................................................................................... 152 10. electrical characteristics .............................................................. 153 10.1. dc c haracteristics .......................................................................................... 153 10.1.1. absolute maximum ratings .......................................................................... 153 10.1.2. recommended operating conditions ........................................................... 153 10.1.3. static characteristics .................................................................................... 153 10.2. a nalog p erformance c haracteristics ......................................................... 154 10.3. s ignal t iming ..................................................................................................... 156 10.3.1. i 2 c control interface .................................................................................... 156 10.3.2. i 2 s/pcm interface master mode .................................................................. 157 10.3.3. i 2 s/pcm interface slave mode ..................................................................... 158 10.3.4. digital microphone interface ....................................................................... 159 11. application circuits ................................................................................ 160 12. package information .............................................................................. 162 12.1. m echanical d imensions ................................................................................... 162 12.2. p ackage t hermal i nformation ...................................................................... 163 13. ordering information ............................................................................ 164
alc5672 datasheet xi rev. 0.75 list of tables t able 1. d igital i/o p ins .......................................................................................................................................................... 9 t able 2. a nalog i/o p ins ........................................................................................................................................................ 10 t able 3. f ilter /r eference ..................................................................................................................................................... 11 t able 4. p ower /g round ......................................................................................................................................................... 11 t able 5. p ower s upply for b est p erformance ................................................................................................................... 13 t able 6. p ower s upply c ondition for p ower d own l eakage .......................................................................................... 13 t able 7. r eset o peration ...................................................................................................................................................... 16 t able 8. p ower -o n r eset v oltage ....................................................................................................................................... 16 t able 9. c lock s etting t able for 48k (u nit : mh z ) .......................................................................................................... 18 t able 10. c lock s etting t able for 44.1k (u nit : mh z ) ..................................................................................................... 18 t able 11. t he relative of sysclk/bclk/lrck ............................................................................................................... 19 t able 12. r egister s ettings for asrc f unction on s lave m ode ................................................................................... 21 t able 13. s ample r ate with filter coefficient for w ind f ilter ..................................................................................... 41 t able 14. a ddress s et ting (0 x 38 h ) ...................................................................................................................................... 43 t able 15. w rite word p rotocol ........................................................................................................................................ 44 t able 16. r ead word p rotocol .......................................................................................................................................... 44 mx - 94 h : jd1 c ontrol ............................................................................................................................................................... 53 mx - bf h : jd1 s tatus ................................................................................................................................................................ . 53 t able 17. r egister m ap .......................................................................................................................................................... 54 t able 18. mx - 00 h : s/w r eset ................................................................................................................................................ 58 t able 19. mx - 02 h : h eadphone o utput c ontrol ................................................................................................................ 58 t able 20. mx - 03 h : line o utput c ontrol ........................................................................................................................... 59 t able 21. mx - 0d h : in1 i nput c ontrol - 1 ........................................................................................................................... 61 t able 22. mx - 0b h : in1 i nput c ontrol - 2 ............................................................................................................................ 61 t able 23. mx - 0c h : in1 i nput c ontrol - 3 ............................................................................................................................ 62 t able 24. mx - 0e h : in2 i nput c ontrol ................................................................................................................................ . 62 t able 25. mx - 0f h : inl & inr v olume c ontrol ................................................................................................................. 63 t able 26. mx - 19 h : dacl1/r1 d igital v olume .................................................................................................................. 64 t able 27. mx - 1a h : dacl2/r2 d igital v olume .................................................................................................................. 64 t able 28. mx - 1b h : dacl2/r2 m ute /u n -m ute c ontrol ................................................................................................... 66 t able 29. mx - 1c h : s tereo 1 adc d igital v olume c ontrol ............................................................................................ 67 t able 30. mx - 1d h : m ono adc d igital v olume c ontrol ................................................................................................ 68 t able 31. mx - 1e h : adc d igital b oost g ain c ontrol ...................................................................................................... 69 t able 32. mx - 1f h : s tereo 2 adc d igital v olume c ontrol ............................................................................................. 70 t able 33. mx - 20 h : m ono adc d igital b oost g ain c ontrol ........................................................................................... 71 t able 34. mx - 26 h : s tereo 2 adc d igital m ixer c ontrol ................................................................................................ 71 t able 35. mx - 27 h : s tereo 1 adc d igital m ixer c ontrol ................................................................................................ 72 t able 36. mx - 28 h : m ono adc d igital m ixer c ontrol .................................................................................................... 73 t able 37. mx - 29 h : s tereo adc to dac d igital m ixer c ontrol .................................................................................... 74 t able 3 8. mx - 2a h : s tereo dac d igital m ixer c ontrol ................................................................................................ . 74 t able 39. mx - 2b h : m ono dac d igital m ixer c ontrol .................................................................................................... 75 t able 40. mx - 2c h : dac d igital m ixer c ontrol ............................................................................................................... 76 t able 41. mx - 2d h : v oice dsp p ath c ontrol 1 .................................................................................................................. 77 t able 42. mx - 2e h : v oice dsp v olume c ontrol ................................................................................................................ 78 t able 43. mx - 2f h : i nterface dac/adc d ata c ontrol ................................................................................................... 79 t able 44. mx - 31 h : s peaker c ontrol 1 ................................................................................................................................ 79 t able 45. mx - 3b h : recmixl c ontrol 1 ............................................................................................................................ 80 t able 46. mx - 3c h : recmixl c ontrol 2 ............................................................................................................................ 80 t able 47. mx - 3d h : recmixr c ontrol 1 ............................................................................................................................ 81 t able 48. mx - 3e h : recmixr c ontrol 2 ............................................................................................................................ 81 t able 49. mx - 45 h : hpomix c ontrol .................................................................................................................................. 82 t able 50. mx - 4f h : outmixl c ontrol ............................................................................................................................... 82
alc5672 datasheet xii rev. 0.75 t able 51. mx - 52 h : outmixr c ontrol 3 ............................................................................................................................ 83 t able 52. mx - 53 h : loutmix c ontrol ............................................................................................................................... 83 t able 53. mx - 61 h : p ower m anagement c ontrol 1 ........................................................................................................... 84 t able 54. mx - 62 h : p ower m anagement c ontrol 2 ........................................................................................................... 85 t able 55. mx - 63 h : p ower m anagement c ontrol 3 ........................................................................................................... 85 t able 56. mx - 64 h : p ower m anagement c ontrol 4 ........................................................................................................... 86 t able 57. mx - 65 h : p ower m anagement c ontrol 5 ........................................................................................................... 87 t able 58. mx - 66 h : p ower m anagement c ontrol 6 ........................................................................................................... 88 t able 59. mx - 6a h : p rivate r egister i ndex ........................................................................................................................ 88 t able 60. mx - 6c h : p rivate r egister d ata ......................................................................................................................... 88 t able 61. mx - 70 h : i2s1 d igital i nterface c ontrol .......................................................................................................... 89 t able 62. mx - 71 h : i2s2 d igital i nterface c ontrol .......................................................................................................... 89 t able 63. mx - 73 h : adc/dac c lock c ontrol .................................................................................................................... 90 t able 64. mx - 74 h : adc/dac hpf c ontrol ........................................................................................................................ 91 t able 65. mx - 75 h : d igital m icrophone c ontrol 1 ........................................................................................................... 92 t able 66. mx - 76 h : d igital m icrophone c ontrol 2 ........................................................................................................... 93 t able 67. mx - 77 h : tdm i nterface c ontrol 1 .................................................................................................................... 94 t able 68. mx - 78 h : tdm i nterface c ontrol 2 .................................................................................................................... 95 t able 69. mx - 79 h : tdm i nterface c ontrol 3 .................................................................................................................... 96 t able 70. mx - 7f h : c lock c ontrol 1 .................................................................................................................................... 97 t able 71. mx - 80 h : g lobal c lock c ontrol ........................................................................................................................ 97 t able 72. mx - 81 h : pll c ontrol 1 ........................................................................................................................................ 98 t able 73. mx - 82 h : p ll c ontrol 2 ........................................................................................................................................ 98 t able 74. mx - 83 h : asrc c ontrol 1 ..................................................................................................................................... 99 t able 75. mx - 84 h : asrc c ontrol 2 ................................................................................................................................... 100 t able 76. mx - 85 h : asrc c ontrol 3 ................................................................................................................................... 101 t able 77. mx - 8a h : asrc c ontrol 4 .................................................................................................................................. 102 t able 78. mx - 8c h : asrc c ontrol 5 .................................................................................................................................. 102 t able 79. mx - 8e h : hp a mp c ontrol 1 ............................................................................................................................... 103 t able 80. mx - 8f h : hp a mp c ontrol 2 ............................................................................................................................... 103 t able 81. mx - 93 h : micbias c ontrol ............................................................................................................................... 104 t able 82. mx - 94 h : jd1 c ontrol ......................................................................................................................................... 104 t able 83. mx - ae h : adc p ath eq c ontrol 1 .................................................................................................................... 105 t able 84. mx - af h : adc p ath eq c ontrol 2 .................................................................................................................... 106 t able 85. mx - b0 h : dac p ath eq c ontrol 1 .................................................................................................................... 107 t able 86. mx - b1 h : eq c ontrol 2 ....................................................................................................................................... 108 t able 87. mx - b2 h : drc c ontrol 1 .................................................................................................................................... 109 t able 88. mx - b3 h : drc c ontrol 2 .................................................................................................................................... 109 t able 89. mx - b4 h : drc c ontrol 3 .................................................................................................................................... 110 t able 90. mx - b5 h : drc c ontrol 4 .................................................................................................................................... 111 t able 91. mx - b6 h : drc c ontrol 5 .................................................................................................................................... 112 t able 92. mx - b7 h : drc c ontrol 6 .................................................................................................................................... 113 t able 93. mx - bb h : j ack d etection c ontrol 1 ................................................................................................................ 113 t able 94. mx - bd h : irq c ontrol 1 ..................................................................................................................................... 114 t able 95. mx - be h : irq c ontrol 2 ..................................................................................................................................... 115 t able 96. mx - bf h : irq c ontrol 3 ..................................................................................................................................... 116 t able 97. mx - c0 h : gpio c ontrol 1 ................................................................................................................................... 117 t able 98. mx - c1 h : gpio c ontrol 2 ................................................................................................................................... 117 t able 99. mx - c2 h : gpio c ontrol 3 ................................................................................................................................... 118 t able 100. mx - cf h : s ounz r eal tm b ass b ack c ontrol ................................................................................................... 119 t able 101. mx - d0 h : s ounz r eal tm t ru t reble c ontrol 1 .............................................................................................. 119 t able 102. mx - d1 h : s ounz r eal tm l t ru t reble c ontrol 2 ............................................................................................ 120 t able 103. mx - d3 h : s tereo 1 adc w ind f ilter c ontrol 1 ............................................................................................ 120 t able 104. mx - d4 h : s tereo 1 adc w ind f ilter c ontrol 2 ............................................................................................ 121 t able 105. mx - d9 h : s oft v olume & zcd c ontrol 1 ...................................................................................................... 122
alc5672 datasheet xiii rev. 0.75 t able 106. mx - da h : s oft v olume & zcd c ontrol 2 ...................................................................................................... 123 t able 107. mx - db h : i nline c ommand c ontrol 1 ............................................................................................................ 123 t able 108. mx - dc h : i nline c ommand c ontrol 2 ............................................................................................................ 124 t able 109. mx - dd h : i nline c ommand c ontrol 3 ............................................................................................................ 125 t able 110. mx - e0 h : v oice dsp c ontrol 1 ........................................................................................................................ 125 t able 111. mx - e1 h : v oice dsp c ontrol 2 ........................................................................................................................ 126 t able 112. mx - e2 h : v oice dsp c ontrol 3 ........................................................................................................................ 126 t able 113. mx - e3 h : v oice dsp c ontrol 4 ........................................................................................................................ 126 t able 114. mx - e4 h : v oice dsp c ontrol 5 ........................................................................................................................ 127 t able 115. mx - e5 h : v oice dsp c ontrol 6 ........................................................................................................................ 127 t able 116. mx - ec h : m ono adc w ind f ilter c ontrol 1 ................................................................................................ 127 t able 117. mx - ed h : m ono adc w ind f ilter c ontrol 2 ................................................................................................ 128 t able 118. mx - ee h : s tereo 2 adc w ind f ilter c ontrol 1 ............................................................................................ 128 t able 119. mx - ef h : s tereo 2 adc w ind f ilter c ontrol 2 ............................................................................................. 130 t able 120. mx - f8 h : j ack d etection c ontrol .................................................................................................................. 130 t able 121. mx - f9 h : j ack d etection c ontrol .................................................................................................................. 131 t able 122. mx - fa h : g eneral c ontrol 1 ........................................................................................................................... 131 t able 123. mx - fb h : g eneral c ontrol 2 ........................................................................................................................... 132 t able 124. pr - 3d h : adc/dac reset c ontrol ................................................................................................................ 132 t able 125. pr - a4 h : dac_l eq (l pf2: a 1) .......................................................................................................................... 133 t able 126. pr - a5 h : dac_l eq (lpf2:h0) .......................................................................................................................... 133 t able 127. pr - a6 h : dac_r eq (lpf2: a 1) .......................................................................................................................... 133 t able 128. pr - a7 h : dac_r eq (lpf:h0) ........................................................................................................................... 134 t able 129. pr - ae h : dac_l eq (bpf2: a 1) .......................................................................................................................... 134 t able 130 . pr - af h : dac_l eq (bpf2: a 2) .......................................................................................................................... 134 t able 131. pr - b0 h : dac_l eq (bpf2:h0) .......................................................................................................................... 134 t able 132. pr - b1 h : dac_r eq (bpf2: a 1) .......................................................................................................................... 135 t able 133. pr - b2 h : dac_r eq (bpf2: a 2) .......................................................................................................................... 135 t able 134. pr - b3 h : dac_r eq (bpf2:h0) ......................................................................................................................... 135 t able 135. pr - b4 h : dac_l eq (bpf3: a 1) .......................................................................................................................... 135 t able 136. pr - b5 h : dac_l eq (bpf3: a 2) .......................................................................................................................... 136 t able 137. pr - b6 h : dac_l eq (bpf3:h0) .......................................................................................................................... 136 t able 138. pr - b7 h : dac_r eq (bpf3: a 1) .......................................................................................................................... 136 t able 139. pr - b8 h : dac_r eq (bpf3: a 2) .......................................................................................................................... 136 t able 140. pr - b9 h : dac_r eq (bpf3:h0) ......................................................................................................................... 137 t able 141. pr - ba h : dac_l eq (bpf4: a 1) ......................................................................................................................... 137 t able 142. pr - bb h : dac_l eq (bpf4: a 2) .......................................................................................................................... 137 t able 143. pr - bc h : dac_l eq (bpf4:h0) ......................................................................................................................... 137 t able 144. pr - bd h : dac_r eq (bpf4: a 1) ......................................................................................................................... 138 t able 145. pr - be h : dac_r eq (bpf4: a 2) .......................................................................................................................... 138 t able 146. pr - bf h : dac_r eq (bpf4:h0) ......................................................................................................................... 138 t able 147. pr - c0 h : dac_l eq (hpf1: a 1) .......................................................................................................................... 138 t able 148. pr - c1 h : dac_l eq (hpf1:h0) ......................................................................................................................... 139 t able 149. pr - c2 h : dac_r eq (hpf1: a 1) .......................................................................................................................... 139 t able 150. pr - c3 h : dac_r eq (hpf1:h0) ......................................................................................................................... 139 t able 151. pr - c4 h : dac_l eq (hpf2: a 1) .......................................................................................................................... 139 t able 152. pr - c5 h : dac_l eq (hpf2: a 2) .......................................................................................................................... 140 t able 153. pr - c6 h : dac_l eq (hpf2:h0) ......................................................................................................................... 140 t able 154. pr - c7 h : dac_r eq (hpf2: a 1) .......................................................................................................................... 140 t able 155. pr - c8 h : dac_r eq (hpf2: a 2) .......................................................................................................................... 140 t able 156. pr - c9 h : dac_r eq (hpf2:h0) ......................................................................................................................... 141 t able 157. pr - ca h : dac_l eq p re -v olume c ontrol .................................................................................................... 141 t able 158. pr - cb h : dac_r eq p re -v olume c ontrol .................................................................................................... 141 t able 159. pr - cc h : dac_l eq p ost -v olume c ontrol ................................................................................................... 142 t able 160. pr - cd h : dac_r eq p ost -v olume c ontrol .................................................................................................. 142
alc5672 datasheet xiv rev. 0.75 t able 161. pr - ce h : adc eq (lpf: a 1) ................................................................................................................................ 142 t able 162. pr - cf h : adc eq (lpf:h0) ................................................................................................................................ 143 t able 163. pr - d0 h : adc eq (bpf1: a 1) .............................................................................................................................. 143 t able 164. pr - d1 h : adc eq (bpf1: a 2) .............................................................................................................................. 143 t able 165. pr - d2 h : adc eq (bpf1:h0) .............................................................................................................................. 143 t able 166. pr - d3 h : adc eq (bpf2: a 1) .............................................................................................................................. 1 44 t able 167. pr - d4 h : adc eq (bpf2: a 2) .............................................................................................................................. 144 t able 168. pr - d5 h : adc eq (bpf2:h0) .............................................................................................................................. 144 t able 169. pr - d6 h : adc eq (bpf3: a 1) .............................................................................................................................. 144 t able 170. pr - d7 h : adc eq (bpf3: a 2) .............................................................................................................................. 145 t able 171. pr - d8 h : adc eq (bpf3:h0) .............................................................................................................................. 145 t able 172. pr - d9 h : adc eq (bpf4: a 1) .............................................................................................................................. 145 t abl e 173. pr - da h : adc eq (bpf4: a 2) .............................................................................................................................. 145 t able 174. pr - db h : adc eq (bpf4:h0) ............................................................................................................................. 146 t able 175. pr - dc h : adc eq (hpf1: a 1) .............................................................................................................................. 146 t able 176. pr - dd h : adc eq (hpf1:h0) ............................................................................................................................. 146 t able 177. pr - e1 h : adc eq p re -v olume c ontrol .......................................................................................................... 146 t able 178. pr - e2 h : adc eq p ost -v olume c ontrol ........................................................................................................ 147 t able 179. pr - e5 h : dac_l b iquad eq (bpf1: h 0- 1) .......................................................................................................... 147 t able 1 80. pr - e6 h : dac_l b iquad eq (bpf1: h 0- 2) .......................................................................................................... 147 t able 181. pr - e7 h : dac_l b iquad eq (bpf1: b 1- 1) .......................................................................................................... 147 t able 182. pr - e8 h : dac_l b iqua d eq (bpf1: b 1- 2) .......................................................................................................... 148 t able 183. pr - e9 h : dac_l b iquad eq (bpf1: b 2- 1) .......................................................................................................... 148 t able 184. pr - ea h : dac_l b iquad eq (bpf1: b 2- 2) ......................................................................................................... 148 t able 185. pr - eb h : dac_l b iquad eq (bpf1: a 1- 1) ......................................................................................................... 148 t able 186. pr - ec h : dac_l b iquad eq (bpf1: a 1- 2) ......................................................................................................... 149 t able 187. pr - ed h : dac_l b iquad eq (bpf1: a 2- 1) ......................................................................................................... 149 t able 188. pr - ee h : dac_l b iquad eq (bpf1: a 2- 2) ......................................................................................................... 149 t able 189. pr - ef h : dac_r b iquad eq (bpf1: h 0- 1) ......................................................................................................... 149 t able 190. pr - f0 h : dac_r b iquad eq (bpf1: h 0- 2) .......................................................................................................... 150 t able 191. pr - f1 h : dac_r b iquad eq (bpf1: b 1- 1) .......................................................................................................... 150 t able 192. pr - f2 h : dac_r b iquad eq (bpf1: b 1- 2) .......................................................................................................... 150 t able 193. pr - f3 h : dac_r b iquad eq (bpf1: b 2- 1) .......................................................................................................... 150 t able 194. pr - f4 h : dac_r b iquad eq (bpf1: b 2- 2) .......................................................................................................... 151 t able 195. pr - f5 h : dac_r b iquad eq (bpf1: a 1- 1) .......................................................................................................... 151 t able 196. pr - f6 h : dac_r b iquad eq (bpf1: a 1- 2) .......................................................................................................... 151 t able 197. pr - f7 h : dac_r b iquad eq (bpf1: a 2- 1) .......................................................................................................... 151 t able 198. pr - f8 h : dac_r b iquad eq (bpf1: a 2- 2) .......................................................................................................... 152 t able 199. mx - fe h : v endor id ........................................................................................................................................... 152 t able 200 . a bsolute m aximum r atings ............................................................................................................................ 153 t able 201. r ecommended o perating c onditions ............................................................................................................. 153 t able 202. s tatic c haracteristics .................................................................................................................................... 153 t able 203. a nalog p erformance c haracteristics ......................................................................................................... 154 t able 204. i 2 c t iming ............................................................................................................................................................ 156 t able 205. t iming of i 2 s/pcm m aster m ode ..................................................................................................................... 157 t able 206. i 2 s/pcm s lave m ode t iming ............................................................................................................................. 158 t able 207. d igital m icrophone i nt erface t iming ........................................................................................................... 159 t able 208. t hermal i nformation ....................................................................................................................................... 163 t able 209. o rdering i nformation ...................................................................................................................................... 164
alc5672 datasheet xv rev. 0.75 li st of figures f igure 1. b lock d iagram ....................................................................................................................................................... 5 f igure 2. a udio m ixer p ath ................................................................................................................................................... 6 f igure 3. d igital m ixer p ath ................................................................................................................................................ 7 f igure 4. p in a ssignments ...................................................................................................................................................... 8 f igure 5. g eneral s ystem c onnection .............................................................................................................................. 12 f igure 6. p ower o n /o ff t iming ........................................................................................................................................... 15 f igure 6. a udio c lock t ree ................................................................................................................................................. 17 f igure 7. s ystem c onnection for asrc f unction ........................................................................................................... 20 f igure 8. pcm mono d ata m ode a f ormat (bclk polarity=0) .............................................................................. 22 f igure 9. pcm mono d ata m ode a f ormat (bclk polarity=1) .............................................................................. 22 f igure 10. pcm mono d ata m ode b f ormat (bclk polarity=0) ............................................................................ 23 f igure 11. pcm s tereo d ata m ode a f ormat (bclk polarity=0) ............................................................................ 23 f igure 12. pcm tdm d ata m ode a f ormat (bclk polarity=0) ............................................................................... 23 f igure 13 . pcm s tereo d ata m od e b f ormat (bclk polarity=0) .............................................................................. 24 f igure 14. pcm tdm d ata m ode b f ormat (bclk polarity=0) ................................................................................. 24 f igure 15. i 2 s d ata f ormat (bclk po larity=0) ............................................................................................................. 24 f igure 16. i 2 s tdm d ata f ormat (bclk polarity=0) ................................................................................................... 25 f igure 17. l eft -j ustified d ata f ormat (bclk polarity=0) ........................................................................................ 25 f igure 18. l eft -j ustified tdm d ata f ormat (bclk polarity=0) ............................................................................... 25 f igure 19. 4-c hannel r ecording p ath ................................................................................................................................ 26 f igure 20. 4-c hannel p layback p ath .................................................................................................................................. 27 f igure 21. s tereo btl s peaker o utput ............................................................................................................................... 30 f igure 22. dac drc f unction b lock .................................................................................................................................. 34 f igure 23. adc agc f unction b lock .................................................................................................................................. 34 f igure 24. drc/agc for p layback /r ecording m ode ....................................................................................................... 38 f igure 25. drc/agc for n oise g ate m ode ......................................................................................................................... 39 f igure 26. d ata t ransfer o ver i 2 c c ontrol i nterface ................................................................................................... 43 f igure 27. gpio f unction b lock .......................................................................................................................................... 45 f igure 28. irq f unction b lock ............................................................................................................................................. 46 f igure 29. p ower m anagement ............................................................................................................................................. 50 f igure 30. i 2 c c ontrol i nterface ....................................................................................................................................... 156 f igure 31. t iming of i 2 s/pcm m aster m ode ...................................................................................................................... 157 f igure 32. i 2 s/pcm s lave m ode t iming ............................................................................................................................. 158 f igure 33. d igital m icrophone i nterface t iming ............................................................................................................ 159 f igure 34. a pplication c ircuit ........................................................................................................................................... 161 f igure 35. p ackage d imension ............................................................................................................................................ 162
alc5672 datasheet 1 rev. 0.73 1. general description the alc5672 is a high performance, low power, dual i 2 s interface audio codec with embedded low power/high performance voice dsp. dual i 2 s interface can connect to different devices and let the alc5672 to be an audio hub. each device can pass through the audio hub and then perform as input or output application. asynchronous sample rate converter (asrc) provides independent and asynchronous connections to different processors, such as an application processor, baseband processor or wireless transceiver(bt). stereo class- d speaker amplifiers provide 1.5w per channel into 8 or 2. 8w per chan nel into 4 with a 5v supply, with high thd+n performance, excellent psrr and low emi. a mono differential earpiece amplifier is also provided, providing output from any dac or analog-in. the alc5672 features an ultra low power cap-free headphone amplifier. it consumes only less than 5mw power during playback, providing mobile system longer battery life under headphone listening mode. the integrated multi-section drc(dynamic range controller) and 14-band parametric equalizer provide further digital sound processing capability of audio playback paths. the multi-section drc in alc5672 continuously monitors the dac output level. when the power level is low, it increases the input signal gain to make it sound louder. at the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard clipping. it ensures the maximum/consistent signal amplitude without producing audio clipping and speaker damage. the 14-band parametric equalizer contains each channel has 7 independent filters with programmable gain, center frequency and bandwidth to tailor the frequency characteristics of embedded speaker system according to user preferences. for microphone recording, the drc in alc5672 can be used as agc(auto gain controller) to maintain a constant recording volume. besides, a dynamic wind reduction filter is built in on recording path. the filter can detect the level of wind noise and on/off dynamically to keep the recording quality. the alc5672 also integrates independent 6-band parametric equalizer for recording path. they can use to compensate microphone device frequency response. alc5672 embedded a low power, high performance voice processor. the 140mips voice processor provides advanced voice processing features, including exceptional noise suppression, echo cancellation and advanced beam-forming under low power consumption. the voice processor is optimized for advanced voice processing to improve voice quality for voice communication and recording in noisy environments. sounzreal tm post-processing technology is configurable to provide better listening experience. bassback exp tm bring lfe(low frequency effect) to listeners without subwoofer needed. trutreble exp tm adds processed harmonic tones at high frequency, bringing more melody and details for music listening.
alc5672 datasheet 2 rev. 0.75 2. features ? digital super wideband voice dsp ? voice communication enhancement (aec, nsetc.) ? advanced beam-forming (voice tracking) ? stereo far field pick-up recording (48khz sample rate) ? sounzreal tm post-processing ? trutreble ? bassback ? parametric 14 bands equalizer (eq) C each 7 bands for l/r playback path independent control ? parametric 6 bands equalizer (eq) for recording path ? advanced drc with multi-section compressor function for playback/recording path ? sound detection wake up technology ? wind noise reduction filter ? one 24bit/8khz ~ 192khz i2s/pcm/tdm digital interface ? one 24bit/8khz ~ 192khz i2s/pcm digital interface ? digital asynchronous sampling rate converter (asrc) function ? i2c control interface ? 3 stereo digital microphone interfaces ? 4 digital- to -analog converter with 100dba snr ? 2 analog- to -digital converter with 94dba snr ? 2 single-ended analog microphone inputs with pre-amplifiers (+20/24/30/35/40/44/50/52db) and low noise microphone bias ? mic input to adc with 50db boost, snr>66dba, thd+n<-65db ? headset microphone and ground auto switch ? stereo line input ? -84db thd+n (with 0db gain path) ? 94dba snr (with 0db gain path) ? stereo single-ended/mono differential line output ? -85db thd+n (with 0db gain path, 10k ohm loading) ? 100dba snr (with 0db gain path, 10k ohm loading)
alc5672 datasheet 3 rev. 0.75 ? stereo btl (bridge-tied load) class-d amplifier ? 700mw/ch (avdd=1.8v, spkvdd=3.6v, thd+n <= 1%, 8ohm) ? 600mw/ch (avdd=1.8v, spkvdd=3.6v, thd+n <= 0.1%, 8ohm) ? 2.8w/ch (avdd=1.8v, spkvdd=5.0v, thd+n <= 10%, 4ohm) ? 2.3w/ch (avdd=1.8v, spkvdd=5.0v, thd+n <= 1%, 4ohm) ? speaker auto ratio gain and spkvdd detection ? auto ratio gain for avdd=1.8v with spkvdd=3.3v ~ 5.0v ? 4-bit pvdd detection for spkvdd=3.3v ~ 5.0v with avdd=1.8v ? stereo headphone output and without dc blocking capacitors ? 20mw/ch (avdd=cpvdd=1.8v, thd+n <= -80db, 16ohm) ? ultra-low-power for headphone playback ? standby power consumption <=5mw (avdd=dbvdd=cpvdd=1.8v, dcvdd=1.2v, 32ohm, with i2s clock input) ? playback power consumption <=10mw (avdd=dbvdd=cpvdd=1.8v, dcvdd=1.2v, 32ohm, with i2s clock input, po=1mw) ? multiple audio jack insert detection function ? headset in -line multi-function control support ? power management and enhanced power saving ? internal pll can receive wide range clock input ? two adjustable micbias (0.9*micvdd or 0.75*micvdd) ? qfn-48 (6mmx6mm) package
alc5672 datasheet 4 rev. 0.75 3. power/ground operation conditions power type decsription min typ max unit dbvdd digital i/o power 1.71 1.8 3.6 v dcvdd digital core power 1.1 1.2 1.4 v avdd analog power 1.71 1.8 1.9 v micvdd microphone bias power 3.0 3.3 3.6 v cpvdd charge pump power 1.71 1.8 1.9 v spkvddl/r speaker power 3.0 5.0 5.5 v dgnd, agnd, cpgnd, spkgnd, ground 0 v 4. system application ? smart phones ? tablet
alc5672 datasheet 5 rev. 0.75 5. function block and mixer path 5.1. function block adc_1 audio signal processing & voice dsp dac_1 dac_2 digital audio interface (i2s / pcm / tdm) bclk1 lrck1 dacdat1 adcdat1 lout1l/p lout1r/n i 2 c control micbias1 micbias2 pll mclk hpo_l hpo_r cpp2 cpn1 cpvref cpvee agnd dcvdd dgnd adc volume high pass filter dac volume high pass filter cpvdd charge pump cpgnd dmic_scl dmic interface micbias / voltage detection dac_3 analog core ldo digital core micbias1 micbias2 0.9 * micvdd 0.75 * micvdd cpn2 ldo_in cpp1 in2p/inl/dmic1_sda in2n/inr/dmic2_sda/jd2 dac_4 digtial i/o cpvpp micvdd avdd adc_2 inl_vol inr_vol dmic1_l lout speaker driver spo_lp spo_ln scl sda rec mixer dmic1_r dmic2_l dmic2_r bst2 spo_rp bclk2 lrck2 dacdat2 adcdat2 ain dbvdd dacref dmic3_l dmic3_r jd1 jd2 analog jd dmic_sda spo_rn dsp core mic_cap spkvddl spkvddr speaker amp in1p_ring2 in1n_sleeve bst1 vref2 gpio gpio1/irq gpio2 reference voltage figure 1. block diagram
alc5672 datasheet 6 rev. 0.73 5.2. audio mixer path outmixr1 digital block alc/drc eq digital volume hpol recmixl recmixr adc_2 adc_1 dac_l1 dac_l2 dac_r1 filter & digital volume adcdat1 dacdat1 dmic_dat dacl1 dacr1 dacl2 filter & digital volume filter & digital volume filter & digital volume filter & digital volume lout1r/n lout1l/p bst1 bst2 hpol amp bst1 bst2 bst2 bst1 adcdat2 dacdat2 +12 ~ -34.5db, 1.5db/step gain gain gain gain gain gain -18 ~ 0db, 3db/step -18 ~ 0db, 3db/step dac_r2 dacr2 filter & digital volume dacr1 dacl1 vol dacl1 outmixl1 inl1 inr1 bst2 vmid in2n in2p 0/20/24/30/35/40/44/50/52 bst2 -34.5~+12db,1.5db/step inl1 -34.5~+12db,1.5db/step inr1 vol inl1 inr1 vol +12 ~ -34.5db, 1.5db/step inl1 dacl1 gain hpvoll 0 / -6db hpvoll hpmixl hpor hpor amp +12 ~ -34.5db, 1.5db/step dacr1 vol inr1 dacr1 gain hpvolr 0 / -6db hpvolr hpmixr outvoll1 dacl1 gain outvoll1 0 / -6db dacr1 gain outvolr1 0 / -6db outvolr1 lout1 +12 ~ -34.5db, 1.5db/step dacl2 dacr2 spoln spolp sporn sporp spkout bst1 vmid in1n_sleeve in1p_ring2 0/20/24/30/35/40/44/50/52 bst1 mx0e[7] mx0e[15:12] mx0f[12:8] mx0f[4:0] mx3c[1] mx3c[3] mx3c[5] mx3c[15:13] mx3b[6:4] mx3b[12:10] mx3e[1] mx3e[3] mx3e[5] mx3e[15:13] mx3e[6:4] mx3d[12:10] mx45[0] mx45[1] mx02[13:8] mx02[5:0] mx45[2] mx45[3] mx4f[0] mx4f[1] mx4f[4] mx4f[5] mx03[13:8] mx03[5:0] mx52[0] mx52[1] mx52[4] mx52[6] mx45[14] mx45[13] mx45[12] mx02[15] mx02[7] mx45[14] mx45[13] mx45[12] mx03[7] mx03[15] mx53[11] mx53[11] mx53[15] mx53[13] mx53[14] mx53[12] mx30[14] mx30[12] figure 2. audio mixer path
alc5672 datasheet 7 rev. 0.73 5.3. digital mixer path voice dsp rx_0 tx_0 tx_1 rx_1 dacl1 dacl2 dacr1 gain gain gain gain l l r r l r l r l l r r l r l r gain gain gain dacr2 gain gain gain gain gain dac_ mixl dac_ mixr vol vol mono_ dac_ mixer_l mono_ dac_ mixer_r adc_1 adc_2 digital interface with tdm gain gain gain gain gain _ gain _ lr ll rr rl dsp up link bypass dacdat2 adcdat2 dacdat1 adcdat1 bypass 2 3 adc_1 adc_2 dac_ mixl dac_ mixr mono_ dac_ mixer_l mono_ dac_ mixer_r slot select dmic_l1 dmic_l2 dmic_r1 dmic_r2 adc_2 dmic_l1 dmic_l2 dmic_r1 dmic_r2 dac_ mixl dac_ mixr dac_ mixl dac_ mixr dmic_l1 dmic_l2 dmic_r1 dmic_r2 digital interface 2 dac_mixl dac_mixr boost gain boost gain boost gain stereo2_adc_mixer_r stereo2_adc_mixer_l stereo1_adc_mixer_r stereo1_adc_mixer_l if1_dac1_l vol vol dacl1 dacr1 dacl2 dacr1 dacl1 dacr2 dacl1dacl2 dacr2 dacr1 dacr2 dacl2 stereo_dac_mixl stereo_dac_mixl dacl2 dacr2 dacl2 dacr2 dacl2 dacr2 if1_dac2_l if2_dac_l txdc_dac_l if2_dac_r txdc_dac_r txdc_dac dsp down link bypass bypass 3 2 (l+r)/2 mono_adc_mixer_r mono_adc_mixer_l stereo2_adc_mixer_l stereo2_adc_mixer_r stereo1_adc_mixer_r stereo1_adc_mixer_l mono_adc_mixer_l mono_adc_mixer_r if1_dac2_l if1_dac2_r if2_dac_l if2_dac_r dacl1 dacr1 if2_dac_r if2_dac_l stereo1_adc_mixer_r stereo1_adc_mixer_l mono_adc_mixer_l mono_adc_mixer_r stereo2_adc_mixer_l stereo2_adc_mixer_r stereo1_adc_mixer_r stereo1_adc_mixer_l mono_adc_mixer_l mono_adc_mixer_r stereo2_adc_mixer_l stereo2_adc_mixer_r if_adc1 if_adc2 if_adc3 if1_dac1_l if1_dac1_r if1_dac2_l if1_dac2_r if1_dac if1_adc if2_dac_l if2_dac_r if2_dac if2_adc if2_adc_l if2_adc_r if_adc1 if_adc2 if_adc3 txdp_adc txdc_dac spk_l spk_r stereo_dac_mixl mono_dac_mixl stereo_dac_mixr mono_dac_mixr txdp_adc txdp_adc_l txdp_adc_r stereo_dac_mixl mono_dac_mixl stereo_dac_mixr mono_dac_mixr dmic_r3 dmic_l3 vol vol stereo1_adc_mixer_l mono_adc_mixer_l mono_adc_mixer_r stereo2_adc_mixer_l vad vad_adc vad_adc vad_adc dmic_l3 dmic_l3 dmic_r3 dmic_r3 if2_dac_l if1_dac1_r if2_dac_r vol vol if_adc2 txdp_adc if_adc1 eq vol boost gain vol boost gain vol boost gain vol alc (share with adc) eq eq dac_spkr dac_spkl data channel control data channel control if_adc3 drc (share with dac) sounzreal adc_1 adc_2 adc_1 adc_2 adc_1 mx27[9:8] mx27[11] mx27[12] mx27[12] mx27[11] mx27[13] mx27[14] mx27[6] mx27[5] mx1e[15:14] mx1e[13:12] mx1c[14:8] mx1c[6:0] mx1c[15] mx1c[7] mx27[9:8] mx28[9:8] mx28[11] mx28[12] mx28[13] mx28[14] mx28[3] mx28[4] mx28[5] mx28[6] mx28[1:0] mx26[9:8] mx26[9:8] mx26[11] mx26[12] mx26[13] mx26[14] mx26[5] mx26[6] mx26[11] mx26[12] mx1e[7:6] mx1e[9:8] mx1f[14:8] mx1f[6:0] mx1f[15] mx1f[7] mx26[15] mx20[15:14] mx20[13:12] mx1d[6:0] mx1d[14:8] mx1d[15] mx1d[7] mx29[9:8] mx29[11:10] mx19[15:8] mx19[7:0] mx29[4] mx29[6] mx29[7] mx29[15] mx2d[15:13] mx2d[12:11] mx2d[0] mx2d[0] mx2d[1] mx2d[1] mx2d[7:6] mx2d[3:2] mx2e[14:8] mx2e[6:0] mx2d[5:4] mx1b[2:0] mx1b[6:4] mx1a[7:0] mx1a[15:8] mx1b[13] mx1b[12] mx2a[14] mx2a[9] mx2a[12] mx2a[13] mx2a[8] mx2a[11] mx2a[6] mx2a[1] mx2a[4] mx2a[5] mx2a[0] mx2a[3] mx2b[14] mx2b[12] mx2b[10] mx2b[13] mx2b[11] mx2b[9] mx2b[6] mx2b[4] mx2b[2] mx2b[1] mx2b[3] mx2b[5] mx2c[15] mx2c[13] mx2c[7] mx2c[6] mx2c[12] mx2c[14] mx2c[11] mx2c[5] mx2c[9] mx2c[8] mx2c[4] mx2c[10] mx30[15] mx30[13] mx30[14] mx30[12] mx9d[9:8] if_adc1 if_adc3 mxfa[12] mxfa[11] txdp_adc if_adc2 vad_adc mx2f[15] mxfa[10] txdp_adc mx2f[11:10] mx2f[9:8] mx2f[14:12] figure 3. digital mixer path
alc5672 datasheet 8 rev. 0.73 6. pin assignments cpp1 cpvdd agnd lrck1 spo_rn spkvddl loutl/p spo_ln spo_lp loutr/n mclk scl sda bclk1 adcdat2 dacdat2 hpo_l hpo_r cpvee cpvref cpn1 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 xxxxxxx ywwvs (top view) jd1 in1n_sleeve in2n/inr1 vref2 gpio1/irq dcvdd alc5672 bclk2 lrck2 adcdat1 dacdat1 cpvpp cpp2 cpn2 micvdd avdd micbias1 gpio2/dmic_scl spkvddr spo_rp in2p/inl1 in1p_ring2 dbvdd dacref cpgnd mic_cap micbias2 spkgndr figure 4. pin assignments
alc5672 datasheet 9 rev. 0.75 7. pin descriptions 7.1. digital i/o pins table 1. digital i/o pins name type pin description characteristic definition dacdat1 i 34 first i2s interface serial data input schmitt trigger (v il =0.35*dbvdd, v ih =0.65*dbvdd) adcdat1 o 35 first i2s interface serial data output v ol =0.1*dbvdd, v oh =0.9*db vdd bclk1 i/o 37 first i2s interface serial bit clock master: v ol =0.1*dbvdd, v oh =0.9*dbvdd slave: schmitt trigger (v il =0.35*dbvdd, v ih =0.65*dbvdd) lrck1 i/o 36 first i2s interface synchronous signal master: v ol =0.1*dbvdd, v oh =0.9*dbvdd slave: schmitt trigger (v il =0.35*dbvdd, v ih =0.65*dbvdd) dacdat2 i 32 multi-function pin: second i2s interface serial data input gpio function digital microphone 3 data input schmitt trigger (v il =0.35*dbvdd, v ih =0.65*dbvdd) adcdat2 o 33 multi-function pin: second i2s interface serial data output gpio function digital microphone 1 data input v ol =0.1*dbvdd, v oh =0.9*db vdd bclk2 i/o 31 multi-function pin: second i2s interface serial bit clock gpio function master: v ol =0.1*dbvdd, v oh =0.9*dbvdd slave: schmitt trigger (v il =0.35*dbvdd, v ih =0.65*dbvdd) lrck2 i/o 30 multi-function pin: second i2s interface synchronous signal gpio function master: v ol =0.1*dbvdd, v oh =0.9*dbvdd slave: schmitt trigger (v il =0 .35*dbvdd, v ih =0.65*dbvdd) sda i/o 40 i2c interface serial data open drain structure scl i 39 i2c interface clock input schmitt trigger mclk i 38 i2s interface master clock input schmitt trigger (v il =0.35*dbvdd, v ih =0.65*dbvdd) gpio1/irq i/o 41 multi-function pin: general purpose input and output interrupt output output: v ol =0.1*dbvdd, v oh =0.9*dbvdd input: schmitt trigger gpio 2/ dmic_scl i/o 42 multi-function pin: general purpose input and output digital microphone clock output output: v ol =0.1*dbvdd , v oh =0.9*dbvdd input: schmitt trigger total: 13 pins
alc5672 datasheet 10 rev. 0.75 7.2. analog i/o pins table 2. analog i/o pins name type pin description characteristic definition loutr/n o 29 line output type single-ended output, right channel differential output, negative channel analog output loutl/p o 28 line output type single-ended output, left channel differential output, positive channel analog output in2p/inl1 i 4 multi-function pin: positive differential input for analog microphone 2 left channel line input digital microphone 1 data input analog input digital input in2n/inr1 i 5 multi-function pin: negative differential input for analog microphone 2 right channel line input second jack detection pin digital microphone 2 data input analog input jd threshold: v il = 0.2v, v ih = 1.2v digital input in1p_ring2 i 11 positive differential input for analog microphone 1 analog input in1n_sleev e i 12 negative differential input for analog microphone 1 analog input jd1 i 16 analog jack detection function multi-level jack detection pin jd threshold: v t1 = 1.485v v t2 = 1.95v v t3 = 2.7v hpo_r o 19 headphone amplifier output right channel analog output hpo_l o 18 headphone amplifier output left channel analog output sp o_ lp o 1 speaker amplifier output left differential positiv e output channel analog output sp o_ln o 48 speaker amplifier output left differential negative output channel analog output spo_rp o 45 speaker amplifier output right differential positive output channel analog output spo_rn o 44 speaker amplifier output right differential negative output channel analog output total: 13 pins
alc5672 datasheet 11 rev. 0.75 7.3. filter/reference table 3. filter/reference name type pin description characteristic definition micbias1 o 13 bias voltage output for microphone programmable analog dc output mic_cap - 14 microphone input reference voltage 4.7uf capacitor to analog ground micbias2 o 9 bias voltage output for microphone programmable analog dc output vref2 o 8 second internal reference voltage 4.7uf capacitor to analog ground dacref o 7 dac/adc reference voltage 4.7uf capacitor to analog ground cpvref - 17 headphone reference ground headphone ground cpn1 - 23 first charge pump bucket capacitor 2.2uf capacitor to cpp1 cpp1 - 22 first charge pump bucket capacitor 2.2uf capacitor to cpn1 cpn2 - 26 second charge pump bucket capacitor 2.2uf capacitor to cpp2 cpp2 - 25 second charge pump bucket capacitor 2.2uf capacitor to cpn2 total: 10 pins 7.4. power/ground table 4. power/ground name type pin description characteristic definition micvdd p 15 analog power for micbias 3.0v ~ 3.3v (default 3.3v is recommended) avdd p 6 analog power 1.71v ~ 1.9v (default 1.8v is recommended) agnd p 10 analog ground cpvdd p 21 analog power for headphone charge pump 1.71v ~ 1.9v (default 1.8v is recommended) cpgnd p 24 analog ground for headphone charge pump cpvee p 27 charge pump negative voltage output 2.2uf capacitor to analog ground cpvpp p 20 charge pump positive voltage output 2.2uf capacitor to analog ground dcvdd p 3 digital power for digital core. (internal ldo generated) 1. 1 v~ 1.3v dbvdd p 2 digital power for digital i/o buffer 1.71v~3.3v (default 1.8v is recommended) spkvddl p 47 speaker amp power for left channel 3.0v~5.0v (default 5v or 3.3v) spkvddr p 43 speaker amp power for right channel 3.0v~5.0v (default 5v or 3.3v) spkgnd/ dgnd p 46, 49* speaker amp ground digital ground exposed-pad total: 12 pins
alc5672 datasheet 12 rev. 0.75 8. function description 8.1. system connection hp-out-l hp-out-r hp-jd micbias1 2.2k 2.2k spo-ln spo-lp spo-rn spo-rp spkgnd spkvddl spkvddr speak power (3.3~5v) speak power (3.3~5v) lout-r lout-l (*used for 3 rd and 4 th speaker output, or speaker amplifier has higher power) to alternative speaker amplifier to alternative speaker amplifier lrck1 bclk1 dacdat1 adcdat1 i2c-scl i2c-sda soc (host) dbvdd digital i/o power (1.8~3.3v) gpio1/irq dacref spkvdd 3.3 ~ 5.0v dcvdd 1uf jd1 hp-jd mic-cap 4.7uf adc adc gpio2/dmic_scl in2n digital microphone 1.8v cpp1 cpn1 2.2uf cpvee 2.2uf vref 4.7uf analog gnd cpgnd digital gnd alc5672 agnd dgnd mclk lrck2 bclk2 dacdat2 adcdat2 cpp2 cpn2 2.2uf cpvpp 2.2uf avdd 1.8v micvdd 3.3v cpvdd 1.8v 4 2 6 5 1 3 in1p in1n 4.7uf 4.7uf figure 5. general system connection
alc5672 datasheet 13 rev. 0.75 9. power there are different power types in alc5672. dbvdd is for digital i/o power, dcvdd is for digital core power, avdd is for analog power, cpvdd is for charge pump power, micvdd is for micbias power and spkvdd is for speaker amplifier power. the power supplier limit condition are dbvdd >= dcvdd and spkvdd >= micvdd > avdd = cpvdd, avdd > dcvdd, and for the best performance, our design setting is shown as below. table 5. power supply for best performance power dbvdd dcvdd avdd cpvdd micvdd spkvdd setting 1.8v 1.2v 1.8v 1.8v 3.3v 5.0v *1.2v dcvdd was generated by internal ldo. to prevent all power down leakage, there are three settings for power supply. at these c onditions, the leakage will be smaller. first setting is to power on all power pin. second setting is to only power on spkvdd and others are removed. the detail setting is shown as following table. table 6 . power supply condition for power down leakage power dbvdd dcvdd avdd cpvdd micvdd spkvdd setting-1 supplied supplied supplied supplied supplied supplied setting-2 n/a n/a n/a n/a n/a supplied setting-3 supplied supplied supplied supplied supplied n/a
alc5672 datasheet 14 rev. 0.75 9.1. power supply on/off sequence to prevent pop noise and make sure function work normally, following power on and off sequence are recommended. case1: for spkvdd is from battery: power on sequence: 1. spkvdd power supply on 2. dbvdd/avdd/cpvdd=1.8v power supply on 3. dbvdd power supply on (this step is required if dbvdd is supplied higher than 1.8v) 4. micvdd power supply on 5. initialize voice dsp of alc5672. 6. power down voice dsp of alc5672. 7. s/w driver start to initial codec settings. power off sequence: 1. power down voice dsp of alc5672. 2. power down all codec function (write 0x0000h to register mx - 00h) 3. micvdd power supply off 4. dbvdd power supply off (this step is required if dbvdd is supplied higher than 1.8v) 5. dbvdd/avdd/cpvdd=1.8v power supply off 6. spkvdd power supply off
alc5672 datasheet 15 rev. 0.75 case2: for spkvdd is from pmic: power on sequence: 1. spkvdd power supply on 2. dbvdd/avdd/cpvdd=1.8v power supply on 3. dbvdd power supply on (this step is required if dbvdd is supplied higher than 1.8v) 4. micvdd power supply on 5. initialize voice dsp of alc5672. 6. power down voice dsp of alc5672. 7. s/w driver start to initial codec settings. power off sequence: 1. power down voice dsp of alc5672. 2. power down a ll codec function (write 0x0000h to register mx - 00h) 3. micvdd power supply off 4. dbvdd power supply off (this step is required if dbvdd is supplied higher than 1.8v) 5. dbvdd/avdd/cpvdd=1.8v power supply off 6. spkvdd power supply off > 300ms spkvdd dbvdd=avdd=cpvdd=1.8v if dbvdd=3.3v micvdd=3.3v codec initial > 200ms figure 6. power on/off timing
alc5672 datasheet 16 rev. 0.75 9.2. reset there are 2 types of reset operation: power on reset (por) and register reset. table 7. reset operation reset type trigger condition codec response por monitor digital power supply voltage reach v por reset all hardware logic and all registers to default values. register reset write mx - 00h reset all registers to default values except some specify control registers and logic. 9.2.1. power-on reset (por) when powered on, d cv dd passes through the v por band of the alc5672 (v por_on ~v por_off ). a power on r eset (por) will generate an internal reset signal (por reset low) to reset the whole chip. table 8. power-on reset voltage symbol min typical max unit v por_on - 0.9 - v v por_off - 0.5 - v note: 1. v por_off must be below v por_on 2. t o c = 25 o c 3. when dcvdd is supplied 1.2v 9.2.2. software reset when mx -00h is wrote, all registers become to default value.
alc5672 datasheet 17 rev. 0.75 9.3. clocking the system clock of alc5672 can be selected from mclk or pll. mclk is always provided externally while the reference clock of pll can be selected from mclk, bclk1/2. the driver should arrange the clock of each block and setup each divider. the clk_sys_i2s1=256*fs provides clocks into stereo dac/adc filter that can be selected from mclk or pll. refer to figure 5. audio sysclk the clk_sys_i2s2=256*fs provides clocks into mono dac/adc filter that can be selected from mclk, pll, refer to figure 5. audio sysclk when enable asrc (asynchronous sample rate converter) function, the clock sources from mclk and bclk1 (or bclk2) are allowed to be asynchronous. the realtek asrc technology can ensure data accuracy and keep audio performance under clock source asynchronous. when alc5672 at master mode, the clock source from mclk will be divided and be sent to external device. the ratio of bclk and lrck can set by register C mx -73. pll mclk clk_sys_i2s1(256fs) (slave) lrck1(slave) mclk pll lrck2 mx80[15:14] mx80[13:11] mx80[3] mx73[14:12] system clock lrck1 lrck1(master) master mode lrck/bclk ratio lrck2(slave) lrck2(master) bclk2 bclk1 bclk1(master) bclk2(master) div_f2 clk_sys_i2s2(256fs) mx73[10:8] inter. clock 2 div_f1 (slave) mx70[15] mx71[15] mx70[15] mx71[15] mx81 & mx82 mx73[15] filter_clk1 (256fs) clk_sys_i2s2(256fs) master mode lrck/bclk ratio mx73[11] figure 6. audio clock tree
alc5672 datasheet 18 rev. 0.75 9.3.1. phase-locked loop a phase-locked loop (pll) is used to provide a flexible input clock from 2.048mhz to 40mhz. the source of the p ll can be set to mclk, bclk1 or bclk2 by setting register. the s/w driver can set up the pll to output a frequency to match the requirement of system clock. the pll transmit formula as below: f out = (mclk * (n+2)) / ((m+2) * (k+2)) {typical k=2} table 9. clock setting table for 48k (unit: mhz) mclk n m f vco k f out 13 66 7 98.222 2 24.555 3.6864 78 1 98.304 2 24.576 2.048 94 0 98.304 2 24.576 4.096 70 1 98.304 2 24.576 12 80 8 98.4 2 24.6 15.36 81 11 98.068 2 24.517 16 78 11 98.462 2 24.615 19.2 80 14 98.4 2 24.6 19.68 78 14 98.4 2 24.6 24 39 8 98.4 2 24.6 table 10. clock setting table for 44.1k (unit: mhz) mclk n m f vco k f out 13 68 8 91 2 22.75 3.6864 72 1 90.931 2 22.733 2.048 86 0 90.112 2 22.528 4.096 64 1 90.112 2 22.528 12 66 7 90.667 2 22.667 15.36 63 9 90.764 2 22.691 16 66 10 90.667 2 22.667 19.2 64 12 90.514 2 22.629 19.68 67 13 90.528 2 22.632 24 62 15 90.352 2 22.588
alc5672 datasheet 19 rev. 0.75 9.3.2. i 2 c and two i 2 s/pcm interface the alc5672 supports i 2 c for the digital control interface, and has two i 2 s/pcm for digital data interface. these two i 2 s/pcm audio digital interfaces are used to send data to 4 dac s or to receive data from a stereo adc. these two i 2 s/pcm audio digital interfaces can be configured to master mode or slave mode. master mode under master mode, bclk and lrck are configured as output. if i2s sysclk is selected from mclk source, sel_sysclk1 (mx- 80[15:14]) should set as 00b . if selected from pll output, sel_sysclk1 should set as 01b. plls source is suggested to provide frequency fr om 2.048mhz to 40mhz. the driver should set each divider ( mx -77 & mx -73) to arrange the clock distribution. refer to figure5. audio clock tree, for details. table 11. the relative of sysclk/bclk/lrck register settings mclk bclk lrck mx - 77[11:10]=00b, i2 s1 mx -73[11 ]=0b , i2s2 256*fs=12.288mhz 32*fs=1.536mhz fs=48khz mx - 77[11:10]=11b, i2s1 mx -73[11 ]=1b , i2s2 256*fs=12.288mhz 64*fs=3.072mhz fs=48khz mx - 77[11:10]=00b, i2s1 mx -73[11 ]=0b , i2s2 256*fs=11.2896mhz 32*fs=1.4112mhz fs=44.1khz mx -77[11:10]=11 b, i2s1 mx -73[11 ]=1b , i2s2 256*fs=11.2896mhz 64*fs=2.8224mhz fs=44.1khz example for master mode: target format: sample rate: 48 khz channel length: 32 bits lrck=48khz bclk=3.072mhz (64 * 48khz) mclk clock request: mclk=12.288mhz (256 * 48 khz) register settings: set mx- fa[0] to 1 // for mclk input clock getting control set mx- 61[15] to 1 // enable i2s -1 set mx-70 [1 5 ] to 0 // enable master mode set mx-77 [1 1:10 ] to 11 // select 64*fs for bclk in master mode set mx-73[14:1 2] to 000 // select i2s -1 pre-divider
alc5672 datasheet 20 rev. 0.75 slave mode under slave mode bclk and lrck are configured as input. the sysclk can be input from mclk , and bclk can be synchronous or asynchronous to mclk. if the sysclk is selected from bclk, the internal pll should generate 256*fs as internal system clock. and the driver should set each divider to arrange the clock distribution. refer to figure5. audio clock tree, for details. if an asynchronous mclk input for bclk and lrck, you can turn on asrc function for this case. as figure 6 shown, the mclk is from external oscillator that clock is no relation (or asynchronous) with soc and bt or 3g baseband. for the connection for soc and bt can connect directly to codec a nd let codec as slave mode and soc/bt as master mode. for the clock requirement of mclk must large than 512*fs as sysclk that fs is sample rate. if the mclk is smaller than 512*fs, that can use internal pll to generate higher than 512*fs clock. codec i2s-1 as slave mode with asrc i2s-1 as slave mode with asrc osc mclk soc bt/3g bb figure 7. system connection for asrc function
alc5672 datasheet 21 rev. 0.75 table 12. register settings for asrc function on slave mode condition: codec as slave mode mclk = 12mhz frame rate = 64*fs target sample rate (fs) = 48khz item register settings note pll settings mx - 81 = 0x1481h mx - 82 = 0x5000h pll settings to generate 512*fs (24.576mhz) for sysclk i2s-1 to dac1 mx - 83 = 0x8000h mx - 84 = 0x0020h for dac1 playback asrc settings i2s-2 to dac2 mx - 83 = 0x1800h mx - 84 = 0xc000h for dac2 playback asrc settings amic to stereo adc filter to i2s-1 mx - 83 = 0x8000h mx - 84 = 0x0800h for amic to stereo adc filter record asrc settings amic to mono adc filter to i2s-2 mx - 83 = 0x1800h mx - 84 = 0x3800h for amic to mono adc filter record asrc settings dmic1 to stereo adc filter to i2s-1 mx - 83 = 0x8200h for dmic1 to stereo adc filter record asrc settings dmic2 to mono adc filter to i2s-2 mx - 83 = 0x1900h mx - 84 = 0x3800h for dmic2 to mono adc filter record asrc settings
alc5672 datasheet 22 rev. 0.75 9.4. digital data interface 9.4.1. two i 2 s/pcm interface the two i2s/pcm interface can be configured as master mode or slave mode. four audio dat a formats are supported: ? pcm mode ? left justified mode ? i 2 s mode ? tdm mode (max. bclk rate is 12.288mhz) 1 2 n n-1 lrck blck dacdat/ adcdat 1/fs msb lsb figure 8. pcm mono data mode a format (bclk polarity=0) 1 2 n n-1 msb lsb 1/fs lrck blck dacdat/ adcdat figure 9. pcm mono data mode a format (bclk polarity=1)
alc5672 datasheet 23 rev. 0.75 1 2 n n-1 lrck blck dacdat/ adcdat 1/fs msb lsb figure 10 . pcm mono data mode b format (bclk polarity=0) 1 2 3 n n-1 lrck blck dacdat/ adcdat 1/fs msb lsb 1 2 3 n n-1 msb lsb left-channel right-channel figure 11. pcm stereo data mode a format (bclk polarity=0) lrck blck dacdat / adcdat 1/ fs msb lsb channel-1 1 2 ------ n msb lsb 1 2 ------ n msb lsb 1 2 ------ n msb lsb 1 2 ------ n x x x 1 2 msb channel-2 channel-3 channel-8 don t care x figure 12. pcm tdm data mode a format (bclk polarity=0)
alc5672 datasheet 24 rev. 0.75 1 2 3 n n-1 lrck blck dacdat/ adcdat 1/fs msb lsb 1 2 3 n n-1 msb lsb left-channel right-channel figure 13. pcm stereo data mode b format (bclk polarity=0) lrck blck dacdat / adcdat 1/ fs msb lsb channel-1 1 2 ------ n msb lsb 1 2 ------ n msb lsb 1 2 ------ n msb lsb 1 2 ------ n x x x 1 2 msb channel-2 channel-3 channel-8 don t care x x figure 14. pcm tdm data mode b format (bclk polarity=0) 1 2 n n-1 lrck blck dacdat/ adcdat 1/ fs msb lsb 1 2 n n-1 msb lsb left channel right channel figure 15. i 2 s data format (bclk polarity=0)
alc5672 datasheet 25 rev. 0.75 lrck blck dacdat / adcdat msb lsb channel-1 1 2 ------ n msb lsb 1 2 ------ n x x x channel-8 don t care x msb lsb channel-1 1 2 ------ n msb lsb 1 2 ------ n x x x channel-8 don t care x 1/ fs figure 16. i 2 s tdm data format (bclk polarity=0) 1 2 n n-1 lrck blck dacdat/ adcdat 1/ fs msb lsb 1 2 n n-1 msb lsb left channel right channel figure 17. left-justified data format (bclk polarity=0) lrck blck dacdat / adcdat msb lsb channel-1 1 2 ------ n msb lsb 1 2 ------ n x x x channel-8 don t care x msb lsb channel-1 1 2 ------ n msb lsb 1 2 ------ n x x x channel-8 don t care x 1/ fs figure 18. left-justified tdm data format (bclk polarity=0)
alc5672 datasheet 26 rev. 0.75 9.5. audio data path the alc5672 provides 4-channel analog dac s for playback and 2-channel analog adc s for recording. 9.5.1. 2 analog adc s with 6-channel record path there are two analog adc s and with up to 6-channel recording path. you can use two analog microphones pass to analog adcs and four digital microphones to reach 6-channel recording. or use three digital microphone interfaces to reach 6-channel recording. these 6-channe l data can through i2s1 interface for recording. the i2s1 interface supports tdm interface and up to 8-ch, 24-bit/ch recording. the full scale input of analog adc is around 0.55vrms. in order to save power, the left and right analog adc can be powered down separately by setting pow_adc_l (mx-61[2]) and pow_adc_r (mx-61[ 1]). and the volume control of the stereo adc is also separately controlled by ad_gain_l (mx-1c[14:8]) and ad_gain_r (mx-1c[6:0]). dmic1_l dmic2_l analog adc_l ch1 if_adc1_l ch2 dac_mixl dac_mixl dmic1_r dmic2_r analog adc_r dac_mixr dac_mixr dmic1_l dmic2_l analog adc_l ch3 if_adc2_l ch4 mono_dac_mixl dmic1_r dmic2_r analog adc_r mono_dac_mixl mono_dac_mixr mono_dac_mixr dmic3_l dmic3_r dmic3_l dmic3_r dmic1_l dmic2_l analog adc_l ch5 if_adc3_l ch6 dac_mixl dac_mixl dmic1_r dmic2_r analog adc_r dac_mixr dac_mixr dmic3_l dmic3_r if_adc1_r if_adc2_r if_adc3_l if_adc1_l if_adc1_r if_adc2_l if_adc2_r if_adc3_l if_adc3_r tdm format figure 19 . 4-channel recording path
alc5672 datasheet 27 rev. 0.75 9.5.2. 4 dac s with 4-channel playback path there are four analog dacs and with up to 4-channel playback path. two i2s interfaces provide four channels data to analog dacs. and analog dac can output audio signal to speaker output, headphone output or line output. that also can use i2s1 tdm interface to support 4-channel playback. the full scale output of analog dac is around 1vrms at line output port. in order to save power, the four analog dacs can be powered down separately by setting pow_dac_l_1 (mx-61[12]), pow_dac _r_1 (mx-61[11]), pow_dac_l_2 (mx-61[7]) and pow_dac_r_2 (mx-61[6]). and the digital volume control of the four dacs are also separately controlled by vol_dac1_l (mx-19 [1 5:8]), vol_dac1_r (mx-19[7:0]) , vol_mono_dacl (mx-1a[15:8] and vol_mono_dacr (mx-1a[7:0]). ch1 if1_dac i2s1 ch2 ch3 if2_dac i2s2 ch4 analog dacl1 analog dacr1 analog dacl2 analog dacr2 ll rr ch1 if1_dac i2s1 tdm ch2 ch3 i2s1 tdm ch4 analog dacl1 analog dacr1 analog dacl2 analog dacr2 ll rr figure 20 . 4-channel playback path
alc5672 datasheet 28 rev. 0.75 9.5.3. mixers the alc5672 has digital and analog mixers build-in. ? output mixer - outmixl/r the stereo analog mixer can do mixing for dac output and analog input. the mixer output is mainly for headphone output and line output. each input path has its mute control to the mixer block in mx -45. pow_outmixl and pow_outmixr can be used to power on/off outmixl/r ? record mixer C recmixl/r the stereo analog mi xer can do mixing for analog input and outmix output. the mixer output is for adc input. each input path has its mute control to the mixer block in mx -3b ~ mx-3e. pow_recmixl and pow_recmixr can be used to power on/off recmixl/r. ? hp mixer C hpmixl/r the stereo analog mixer can do mixing for headphone volume and dac output. the mixer output directly output to external headphone device. each input path has its mute control to the mixer block in mx-45. ? digital mixer there are twelve digital mixers in alc5672. six digital mixers are assigned for adc recording. these si x mixers can mix analog line input, analog microphone input and digital microphone input then output to i2s interface to other device. another four digital mixers are assigned for dac playback. these mixers can mix digital data from i2s interface or adc data from external analog signal. the mixed data is output to analog dac and output port to drive external device. the other two mixers are used for da-ad processing. the incoming data from two i2s interfaces (dacdat) uses these two mixers to do mixing and output to i2s interface (adcdat).
alc5672 datasheet 29 rev. 0.75 9.6. analog audio input port the alc5672 has two type analog input port s: microphone input and line input. ? in 1p_ring2/in1n_sleeve the port is a microphone type input port. the input port only can be configured as single-ended mode . the microphone input port has its microphone bias and microphone boost. the low noise microphone bias can improve recording performance and enhance recording quality. build- in short current detection scheme can be used for switch detection. multi-steps microphone boost gain set by sel_bst1 (mx-0d[15:12]) is easy to use for microphone application. pow_bst1 can be used to power down the mic1 boost and pow_micbias1 can be used to power down the microphone bias 1. ? in2p/n the in2p/n is a dual type input port: microphone input and line input. microphone input can be configured to differential input or single-ended input by mx-0e[7]. multi-steps microphone boost gain set by sel_bst2 ( mx -0e[15:12]) is easy to use for microphone application. pow_bst2 can be used to power down the mic2 boost. if as line input, it has volume control for tuning by mx-0f[12:8] and mx-0f[4:0].
alc5672 datasheet 30 rev. 0.75 9.7. analog audio output port the alc5672 supports three type output ports: ? spo_l/r_p/n the speaker output of alc5672 is a stereo btl output with class-d type amplifier. the power of speaker amplifier is an individual power pin and higher than avdd. so the input and output of speaker amplifier has a gain ratio to enlarge or reduce the income analog signal. the ratio gain is auto tuning. the input source of the speaker output port can be select ed from stereo_dac_mixl/r or mono_dac_mixl/r. s p k v d d l s p k g n d s p o l p s p k v d d l s p k g n d s p o l n s p k v d d r s p k g n d s p o r p s p k v d d r s p k g n d s p o r n gate drive gate drive gate drive gate drive l p l n r p l n s t e r e o _ d a c _ m i x l m o n o _ d a c _ m i x l s t e r e o _ d a c _ m i x l m o n o _ d a c _ m i x l s t e r e o _ d a c _ m i x r m o n o _ d a c _ m i x r s t e r e o _ d a c _ m i x r m o n o _ d a c _ m i x r figure 21. stereo btl speaker output
alc5672 datasheet 31 rev. 0.75 ? hpo_l/r the headphone output of alc5672 is a stereo output with cap-free type headphone amplifier. it does not need to connect external capacitor and can connect to earphone device directly. the headphone output source can mix from output mixer ( hp mix) and dac by setting mx-45. the front stage of headphone output has volume control and gain control. the volume range is from +12db to -46.5db with 1.5db/step by mx-02. en_l_hp and en_r_hp (mx-63[7/6]) can be used to power on/off headphone amplifier, and pow_hpo_voll and pow_hpo_volr (mx-66[11/10]) can be used to power on/off headphone volume control. in addition, pow_pump_hp (mx-8e[3]) can be used to power on/off charge pump circuit for headphone amplifier. ? line_out_l/r the output type is line type output. the output is a stereo single ended output or mono differential. the input can be selected from outmix or dac output by setting mx-53[15:12]. the front stage of lout output has gain control for attenuation. the gain control is 0db or -6db by mx -53[11]. 9.8. multi-function pins there are eight multi-function pins in alc5672. for different functions of each pin are controlled by register. you need to set the right register settings for each multi-function pins by your application.
alc5672 datasheet 32 rev. 0.75 ? gpio1/irq C pin 41 the pin default is gpio function. it can change to irq output, write mx- c0[15] to 1b will switch to irq function. ? gpio2/dmic_scl C pin 42 the pin default is gpio function. it can change to dmic clock output, write mx- c0[14] to 1b will switch to dmic clock output function. ? in2 p/ inl/dmic1_dat C pin 4 the pin can as analog microphone positive input or as line input. if as analog microphone input function needs to power on the power C mx -64[13] & mx64[4]. if as analog input function needs to power on the power C mx -66[9] & mx66[8]. digital microphone input function: 1. power down analog microphone input and line input. 2. mute in2 to each analog mixer - (recmixlr/outmixlr/hpmixlr). 3. change in2p pin share function, set mx- 75[1:0] to 01b. 4. tu rn on digital microphone function C mx - 75[14] = 1b ? in 2n/inr/dmic2_dat/jd2 C pin 5 there are four functions share this pin. for each function switching shows below: analog microphone input function, power on mx -64[13] & mx-64[4] and power off other functions. analog line input function, power on mx-66[9] & mx-66[8] and power off other functions. digital microphone input function: 1. power down analog microphone input, line input and jd2 function 2. mute in2 to each analog mixer - (recmixlr/outmixlr/ hp mix lr ). 3. change in2n pin share function, set mx- 75[10] to 1b. 4. turn on digital microphone function C mx -75[14 ] = 1b jack detection function: 1. power down analog microphone input, line input and digital microphone function. 2. mute in2 to each analog mixer - (recmixlr/outmixlr/ hp mix lr ). 3. turn on jd 2 power C mx -64 [1] = 1b ? bclk2/gpio3 C pin 31 mx -c0[8] use to control pin31 is bclk2 function or gpio function.
alc5672 datasheet 33 rev. 0.75 ? lrck2/gpio4 C pin 30 mx -c0[8] use to control pin31 is l rc k2 function or gpio function. ? dacdat2/gpio5/dmic3_sd a C pin 32 mx -c0[8] use to control pin31 is lrck2 function or gpio function. mx -c0[7] use to control pin31 is gpio function or dmic_sda3 function. ? adcdat2/gpio6/dmic1_sda C pin 33 mx -c0[8] use to control pin31 is lrck2 function or gpio function. mx -c0[6] use to control pin31 is gpio function or dmic_sda1 function.
alc5672 datasheet 34 rev. 0.73 9.9. drc and ag c function the dynamic range controller (drc) dynamically adjusts the input signal and let the output signal achieve the target level. the alc5672 supports playback drc for dac path, and the drc can also be used as agc(auto gain controller) for adc path. the control register is at mx-b4[15:14]. the function block is shown as below. the signal input pass through the pre-gain first, then drc volume and post-gain then output. the pre- ga in is use to enlarge the input signal. the drc volume is use to attenuate the signal after detected by drc. the post-gain is use to fine tune the signal after pass drc tuning. i2c interface pre-gain drc volume post-gain dac drc -95.625 ~ 0db 0.375/step -11.625 ~ 12db, 0.375/step mxb5[13:8] 0 ~ 28.5db, 1.5/step mxb5[4:0] 1. limiter level 2. attack / release time 3. zero data figure 22. dac drc function block analog pre-boost pre-gain agc volume i2s interface agc -95.625 ~ 0db 0.375/step 1. limiter level 2. attack / release time 3. noise gate adc 0 ~ 28.5db, 1.5/step mxb5[4:0] post-gain -11.625 ~ 12db, 0.375/step mxb5[13:8] figure 23. ad c agc function block
alc5672 datasheet 35 rev. 0.75 drc output curve - playback mode: the figure 24. shows drc output curve for dac playback application. alc_thmax(mx-b7[5:0]): the parameter limits the maximum output level when 0db full scale input. the limit range is from 0dbfs to -23.625dbfs. ratio_1(mx-b5[6:5]): the parameter determines the slope begin from start point. there are 4 slopes can be selected. alc_thmax2(mx-b7[11:6]): the parameter determines the first knee from ratio_1 curve. the range is from 0dbfs to -45dbfs. ratio_2(mx-b5[15:14]): the parameter determines the slope begin from first knee. there are 4 slopes can be selected. the second knee is calculated by internal circuit. it bases on ratio_2 and alc_thmin to calculate. alc_thmin(mx-b2[5:0]): the parameter determines the third knee from previous curve. the range is from -60dbfs to -94.5dbfs. ratio_3(mx-b5[1:0]): the slope is determined by third knee and end point. the end point is determined by boost gain on mx -b3[11:6] register. 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -95.625 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 vout (db) boost_gain = 12db (reg.) alc_thmin = -60db (reg.) alc_thmax=-6db (reg.) alc_thmax2 = -12db (reg.) ration_2=? (reg.) ratio_1=? (reg.) segment1 segment2 segment_thmin knee (h/w) vin (db) ration_3 (h/w) 1:1 boost start point 1 st knee 2 nd knee 3 rd knee end point figure 24 . playback drc output curve
alc5672 datasheet 36 rev. 0.75 drc output curve - record mode 1: the figure 25. shows drc output curve for adc record application. alc_thmax(mx-b7[5:0]): the parameter limits the maximum output level when 0db full scale input. the limit range is from 0dbfs to -23.625dbfs. ratio_1(mx-b5[6:5]): the parameter determines the slope begin from start point. there are 4 slopes can be selected. alc_thmax2(mx-b7[11:6]): the parameter determines the first knee from ratio_1 curve. the range is from 0dbfs to -45dbfs. ratio_2(mx-b5[15:14]): the parameter determines the slope begin from first knee. there are 4 slopes can be selected. the second knee is calculated by internal circuit. it bases on ratio_2 and alc_thnoise to calculate. alc_thnoise(mx-b6[4:0]): the parameter determines the third knee from previous curve. the range is from -24dbfs to -70.5dbfs. noise_gate_ratio(mx-b5[1:0]): the parameter determines the slope begin from third knee. there are 4 slopes can be selected. the end point is determined by third knee and noise_gate_ratio. 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 vout (db) alc_thnoise = -48db (reg.) alc_thmax2 = -12db (reg.) ratio_2=? (reg.) ratio_1=? (reg.) noise_gate_ratio=2 (reg.) segment1 segment2 segment_noise_gate knee (h/w) vin (db) -95.625 alc_thmax=-6db (reg.) boost_gain = 12db (reg.) 1:1 boost start point 1 st knee 2 nd knee 3 rd knee end point figure 25. record drc output curve - 1
alc5672 datasheet 37 rev. 0.75 drc output curve - record mode 2: the figure 26. shows another drc output curve for adc record application. alc_thmax(mx-b7[5:0]): the parameter limits the maximum output level when 0db full scale input. the limit range is from 0dbfs to -23.625dbfs. ratio_1(mx-b5[6:5]): the parameter determines the slope begin from start point. there are 4 slopes can be selected. alc_thmax2(mx-b7[11:6]): the parameter determines the first knee from ratio_1 curve. the range is from 0dbfs to -45dbfs. ratio_2(mx-b5[15:14]): the parameter determines the slope begin from first knee. there are 4 slopes can be selected. the second knee is calculated by internal circuit. it bases on ratio_2 and alc_thnoise to calculate. alc_thnoise(mx-b6[4:0]): the parameter determines the third knee from previous curve. the range is from -24dbfs to -70.5dbfs. from third knee to fourth knee is a noise drop function by enable noise gate drop mode at mx-b5[4]. the drop level is determined by boost_gain (mx-b3[11:6]) and alc_noise_gate_exp (mx-b6[15:12]). noise_gate_ratio(mx-b5[1:0]): the parameter determines the slope begin from fourth knee. there are 4 slopes can be selected. the end point is determined by fourth knee and noise_gate_ratio. 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 vout (db) alc_noise_gate_exp = 6db segment1 segment2 segment_noise_gate vin (db) -95.625 drop_all = 12 + 6 =18db alc_thmax=-6db (reg.) ratio_2=? (reg.) ratio_1=? (reg.) alc_thmax2 = -12db (reg.) knee (h/w) alc_thnoise = -48db (reg.) boost_gain = 12db (reg.) noise_gate_ratio=2 (reg.) boost_gain = 12db start point 1 st knee 2 nd knee 3 rd knee 4 th knee end point figure 26. record drc output curve - 2
alc5672 datasheet 38 rev. 0.75 playback/recording mode: for dac playback or adc recording mode, when the input signal exceeds target threshold, the signal will decrease drc/agc d igital volume (0.375db/step at every zero-crossing) until drop to target level then keep the digital volume. when input signal is below the target threshold, the signal will step-up drc/agc digital volume (0.375db/step every zero -crossing) until return to original level. if want to return to the target level, need to set the pre-gain to achieve. fine tune parameters: ? limiter threshold: 0 ~ -46.5db, 1.5db/step, mx-b7[5:0] ? attack rate: t=(4*2^n)/sample rate, n = mx - b4 [12:8] ? recovery rate: t=(4*2^n)/sample rate, n = mx -b4[4:0] volume 0db input signal output signal target level attack rate recovery rate figure 27. dr c/agc for playback/recording mode
alc5672 datasheet 39 rev. 0.75 noise gate mode: the noise gate function is use to reduce the noise floor for dac path or adc path. when input signal is below noise gate level, the input signal will be reduced by dr c/agc volume in order to suppress the background noise. the reducing level can be set by register. and when input signal is above noise gate, the input signal will be boosted to target level. fine tune parameters: ? noise gate threshold: -36 ~ -82.5db, 1.5db/step, mx-b6[4:0] ? noise gate attack rate: t=(4*2^n)/sample rate, n = pr -06[4:0] ? noise gate recovery rate: t=(4*2^n)/sample rate, n = pr -02[12:8] ? reducing noise level: 0 ~ 45db, 3db/step, mx-b6[15:12] volume 0db input signal output signal target level attack rate recovery rate noise gate attack rate recovery rate noise gate target level noise reduction figure 28. drc/agc for noise gate mode
alc5672 datasheet 40 rev. 0.75 9.10. sounzreal tm post-processing the realteks sounzreal tm post-processing is composed of: ? trutreble ? bassback 9.11. equalizer block the equalizer block cascades 7 bands of equalizer to each channel to tailor the frequency characteristics of embedded speaker system according to user preferences and to emulate environment sound. the 7 bands equalizer includes two high pass filters, three band pass filters, one low pass filter and one biquad filter. one high pass filter cascaded in the front end is used to drop low frequency tone, the tone has a large amplitude and may damage a mini speaker. the high pass filter can be used to adjust treble strength with gain control. one low pass filter with gain control can adjust the bass strength. three bands of band pass filters are used to emulate environment sounds, e.g., pub, live, rock, etc.. the gain, center frequency and bandwidth of each filter are all programmable. one biquad filter can switch to high-pass, low-pass or band-pass filter by register settings. 9.12. wind noise reduction filter the wind filter is implemented by a high pass filter equalizer. the wind filter is mainly for adc recording used. the cut-off freqnecy of wind filter is programmable and is varied accroding to differe nt sample rate. the filter is used to remove dc offset at normal condition, and to remove wind noise at application mode. there are three wind filters for three adc filters: stereo 1 adc wind filter => mx-d3 & mx- d4 mono adc wind filter => mx-ec & mx- ed stereo 2 adc wind filter => mx-ee & mx- ef
alc5672 datasheet 41 rev. 0.75 wind filter setting procedure (for stereo 1 adc filter): step1: disable wind filter C mx -d3[15] step2: select filter coarse coefficient C mx -d3[14:12] and mx-d3[10:8] step3: select filter fine coefficient C mx -d4[13:8] and mx-d4[5:0] st ep 4 : enable wind filter C mx -d3[15] the following table (table 13.) is shown the fc with sample rate selection. for the formula of fc calculation is also shown as: fc = (fs * tan -1 (a/(2-a))) / where: sample rate = 8k/12k/16k (mx-d3[14:12] and [10:8]), a = 2 -6 + n * 2 -6 (n is mx - d4 [1 3:8] & mx-d4[5:0]) sample rate = 24k/32k (mx-d3[14:12] and [10:8]), a = 2 -7 + n * 2 -7 (n is mx-d4[13:8] & mx-d4[5:0]) sample rate = 44.1k/48l (mx-d3[14:12] and [10:8]), a = 2 -8 + n * 2 -8 (n is mx-d4[13:8] & mx-d4[5:0]) sample rate = 88.2k/96l (mx-d3[14:12] and [10:8]), a = 2 -9 + n * 2 -9 (n is mx-d4[13:8] & mx-d4[5:0]) sample rate = 176.4k/192l (mx-d3[14:12] and [10:8]), a = 2 -10 + n * 2 -10 (n is mx-d4[13:8] & mx-d4[5:0]) table 13. sample rate with filter coefficient for wind filter pr -6e[11:6] n l & r channel sample rate setting 8k 16 k 32 k 44.1k 48 k 000000b, 0 20.0 40.1 39.9 27.4 29.8 000001b, 1 40.4 80.8 80.2 55.0 59.9 000010b, 2 61.1 122.2 120.7 82.7 90.0 000011b, 3 82.1 164.2 161.6 110.5 120.3 000100b, 4 103.4 206.9 202.8 138.4 150.6 000101b, 5 125.1 250.2 244.4 166.4 181.1 000110b, 6 147.1 294.3 286.2 194.5 211.7 000111b, 7 169.5 339.0 328.4 222.7 24 2.5 001000b, 8 192.2 384.4 371.0 251.1 273.3 001001b, 9 215.2 430.5 413.8 279.5 304.3 001010b, 10 238.7 477.4 457.0 308.1 335.4 001011b, 11 262.4 524.9 500.5 336.8 366.6 001100b, 12 286.6 573.2 544.4 365.6 397.9 001101b, 13 311.1 622.3 588.6 39 4.5 429.4 001110b, 14 336.0 672.1 633.2 423.5 460.9 001111b, 15 361.3 722.6 678.1 452.6 492.6 010000b, 16 386.9 773.9 723.3 481.9 524.5 010001b, 17 413.0 826.0 768.9 511.2 556.4 010010b, 18 439.4 878.9 814.9 540.7 588.5 010011b, 19 466.2 932.5 861.2 570.3 620.7 010100b, 20 493.5 987.0 907.8 600.0 653.0 010101b, 21 521.1 1042.2 954.9 629.8 685.5 010110b, 22 549.1 1098.2 1002.2 659.7 718.1 010111b, 23 577.5 1155.0 1050.0 689.8 750.8 011000b, 24 606.3 1212.7 1098.1 719.9 783.6 011001b, 25 635.5 1271.1 1146.6 750.2 816.6 011010b, 26 665.1 1330.3 1195.5 780.6 849.6 011011b, 27 695.2 1390.4 1244.7 811.1 882.9
alc5672 datasheet 42 rev. 0.75 pr -6e[11:6] n l & r channel sample rate setting 8k 16 k 32 k 44.1k 48 k 011100b, 28 725.6 1451.2 1294.3 841.8 916.2 011101b, 29 756.4 1512.9 1344.3 872.5 949.7 011110b, 30 787.6 1575.3 1394.7 903 .4 983.3 011111b, 31 819.3 1638.6 1445.4 934.4 1017.0 100000b, 32 851.3 1702.7 1496.5 965.5 1050.9 100001b, 33 883.7 1767.5 1548.0 996.8 1084.9 100010b, 34 916.6 1822.3 1599.9 1028.1 1119.0 100011b, 35 949.8 1899.6 1652.2 1059.6 1153.3 100100b, 36 983.3 1966.7 1704.9 1091.2 1187.7 100101b, 37 1017.3 2034.7 1757.9 1122.9 1222.2 100110b, 38 1051.6 2103.3 1811.4 1154.8 1256.9 100111b, 39 1086.3 2172.7 1865.2 1186.7 1291.7 101000b, 40 1121.4 2242.9 1919.5 1218.8 1326.6 101001b, 41 1156.8 2313.7 1974.1 1251.0 1361.7 101010b, 42 1192.6 2385.2 2029.1 1283.4 1396.9 101011b, 43 1228.7 2457.4 2084.6 1315.8 1432.2 101100b, 44 1265.1 2530.2 2140.4 1348.4 1467.7 101101b, 45 1301.8 2603.6 2196.6 1381.1 1503.3 101110b, 46 1338.8 2677.7 2253. 3 1414.0 1539.0 101111b, 47 1376.1 2752.3 2310.3 1447.0 1574.9 110000b, 48 1413.7 2827.5 2367.7 1480.0 1610.9 110001b, 49 1451.5 2903.1 2425.5 1513.3 1647.1 110010b, 50 1489.6 2979.3 2483.8 1546.6 1683.4 110011b, 51 1528.0 3056.0 2542.4 1580.1 17 19.8 110100b, 52 1566.5 3133.1 2601.5 1613.7 1756.4 110101b, 53 1605.3 3210.6 2660.9 1647.4 1793.1 110110b, 54 1644.2 3288.4 2720.8 1681.3 1830.0 110111b, 55 1683.3 3366.6 2781.0 1715.3 1867.0 111000b, 56 1722.5 3445.1 2841.7 1749.4 1904.1 11100 1b, 57 1761.9 3523.9 2902.7 1783.6 1941.4 111010b, 58 1801.4 3602.9 2964.2 1818.0 1978.8 111011b, 59 1841.0 3682.1 3026.1 1852.5 2016.3 111100b, 60 1880.7 3761.4 3088.3 1887.1 2054.0 111101b, 61 1920.4 3840.8 3151.0 1921.9 2091.9 111110b, 62 196 0.2 3920.4 3214.1 1956.8 2129.9 111111b, 63 2000.0 4000.0 3277.5 1991.8 2168.0
alc5672 datasheet 43 rev. 0.75 9.13. i 2 c control interface i 2 c is a 2-wire (scl/sda) half-duplex serial communication interface, supporting only slave mode. s cl is used for clock and sda is for data. scl clock supports up to 400khz rate and sda data is a open drain structure. the input has built-in spike filter and can remove less than 50ns spike at scl and sda. 9.13.1. address setting table 14. address setting (0x38 h) (msb) bit (lsb) 0 0 1 1 1 0 0 r/w 9.13.2. complete data transfer data transfer over i 2 c control interface figure 29. data transfer over i 2 c control interface
alc5672 datasheet 44 rev. 0.75 write word protocol table 15. write word protocol s device address wr register address data byte high data byte low p a a a a 1 7 1 1 8 1 8 1 8 1 1 read word protocol table 16. read word protocol s device address wr data byte high data byte low p s device address a a rd na a 1 7 1 1 8 1 7 1 8 1 1 8 1 register address a s: start condition a: 0 for ack, 1 for nack slave address: 7-bit device address data byte: 16 -bit mixer data wr : 0 for write command ? : master-to-slave rd : 1 for read command ? : slave- to -master command code: 8-bit register address
alc5672 datasheet 45 rev. 0.75 9.14. gpio, interrupt and jack detection the alc5672 supports six gpio s C gpio1/gpio2/gpio3/gpio4/gpio5/gpio6. for gpio function, the gpio can be configured to input or output. for input type, the internal circuit can read pin status and report to register table. for output type, the internal circuit can drive this pin to high or low to control external device. in gpio function, the pin polarity can be controlled by register at output type. gpio1 mx-c1[1] en_obuf en_ibuf mx-c1[2] high low mx-c1[0] mx-bf[8] gpio2 mx-c1[4] en_obuf en_ibuf mx-c1[5] high low mx-c1[3] mx-bf[7] gpio3 mx-c1[7] en_obuf en_ibuf mx-c1[8] high low mx-c1[6] mx-bf[6] gpio4 mx-c1[10] en_obuf en_ibuf mx-c1[11] high low mx-c1[9] mx-bf[5] gpio5 mx-c1[13] en_obuf en_ibuf mx-c1[14] high low mx-c1[12] mx-bf[9] gpio6 mx-c2[1] en_obuf en_ibuf mx-c2[2] high low mx-c2[0] mx- bf[10] figure 30 . gpio function block for the jack detection function, there are four gpios (gpio3/4/5/6) can be configured as jack detection pins and also have jd1 and jd2 can as jack detection pin. for gpio jack detection pin source selection is controlled by mx-bb[15:13]. its jd status is sta_gpio_jd1 C mx -bf[4]. for jd1, it can detect two ports. which jd statuses are sta_jd1_1 C mx -bf[12] & sta_jd1_2 C mx -bf[13]. for jd2, it can detect one port. which jd status is sta_jd2 C mx -bf[14]. mx-bb[15:13] gpio3 gpio4 gpio5 gpio6 sta_gpio_jd1
alc5672 datasheet 46 rev. 0.75 for irq function as shown at figure 24, the irq output source can be selected from jd1 s tatus, jd2 status, gpio jd status, inline command status and micbias1 over-current status. when either status is trigged, the gpio will output a flag as interrupt signal. sta_jd1_1_internal irq mx-bd[13] sticky control mx-bd[14] mx-bd[15] mx-bb[15:13] gpio3 gpio4 gpio5 gpio6 mx-bd[7] sticky control mx-bd[8] mx-bd[9] mx-bd[4] sticky control mx-bd[5] mx-bd[6] sta_jd1_2_internal mx-bd[1] sticky control mx-bd[2] mx-bd[3] sta_jd2_internal mx-be[11] sticky control mx-be[13] mx-be[15] sta_micbias1_ovcd_internal mx-bf[0] sticky control mx-bf[1] mx-bf[3] sta_inline_command_internal or gate figure 31 . irq function block
alc5672 datasheet 47 rev. 0.75 in general, the irq output needs to combine with jd function. when jd is trigger, irq will output a flag to host to notice s/w driver. the s/w driver will do some settings by system design. the behavior flow chard as following: device plug-in jd triggered initial settings (for jd and irq) irq flag output to host s/w driver settings clear jd status for next jd trigger the micbias supports short current detection function. when micbias circuit detects over-current happen, micbias circuit will generate an over-current flag. the flag can generate an interrupt signal to notice host and let s/w do follow-up processes. the jack detect function can be used to turn-on or turn-off the related output ports. when jack detect pin is trigged, the selected output ports will be turn-on or turn-off. for example on hp and spk auto switch when jd is trigger. setting procedure: 1. select jd status source: use sta_jd1_1 as jd source. mx- f8 [2:0] = 00 1b & mx-f9[11:9] = 0 01b 2. set jd status polarity for hp and spk mx -bb[11:10 ] = 10b , jd status low to trigger hpo mx - bb[9:6] = 1111b, jd status high to trigger spk 3. when jd status is low, hp_out is un-mute and spk is mute. when jd status is low go high, hp is mute and spk is un-mute. note: for hp and spk port switch function, driver need to turn-on dac to hp path and dac to spk path first.
alc5672 datasheet 48 rev. 0.75 9.15. push button detection the alc5672 has built-in push button detection circuit inside. it can supports up to three push buttons. each button support three behaviors and shows on register (mx-dbh) C one click, double click and hold. the push button event will also cause an interrupt to irq output to notice external host. u c d tip ring ring2 sleeve r2 u c d mic ring2 sleeve r1 r3 push button resistance resistance range recommend value u p button, r2 150 ~ 280 ohm 220 ohm c enter button, r1 0 ~ 50 ohm 20 ohm d own button, r3 550 ~ 650 ohm 620 ohm push button detection status: button # button behavior register status u p button one click mx -dbh[15] double click mx -dbh[ 14] hold mx -dbh[13] c enter button one click mx -dbh[12] double click mx -dbh[11] hold mx -dbh[10] d own button one click mx -dbh[9] double click mx -dbh[8] hold mx -dbh[7]
alc5672 datasheet 49 rev. 0.75 push button detection flow chart: push button trigger (press push button) irq output (codec issue a interrupt) initial settings (power-on) status? (codec driver check codec register status) configuration (codec driver set settings by push button event) clear status for next push button trigger
alc5672 datasheet 50 rev. 0.75 9.16. power management alc5672 detailed power management control registers are support ed in mx -61h, 62h, 63h, 64h, 65h and 66h. each particular block will only be active when each bit mx -61h, 62h, 63h, 64h, 65h and 66h is set to enable. mx-61 i2s-1 power i2s-2 power dacl1/r1 power dacl2/r2 power adcl/r power mx-63 analog vref power analog mbias power lout mixer power headphone amp power mx-64 mic bst1 power mic bst2 power micbias1 power pll power mx-65 outmixl power outmixr power recmixl power recmixr power mx-66 hpmixl power hpmixr power inlvol power inrvol power jd power mx-62 dac digital filter adc digital filter dsp power figure 32 . power management
alc5672 datasheet 51 rev. 0.75 9.17. gen.3 voice dsp function the on-chip voice processor provides microphone beam-forming with voice tracking to allow for acoustic echo cancellation, far-field pickup, stationary and non-stationary noise suppression, and voice recognition rate enhancement. data interface control interface voice provessor dual-core dsp sram rom accelerators pll/clock gen power management data input/output command control master clock vdd / vss acoustic echo cancellation: the voice dsp suppresses echo effectively under all occasions, and the performance of which could be easily optimized for different types of acoustics set-up and applications for tablet computers. the aec performs robustly under prolonged double talk periods and provides a face- to -face like conversation in full-duplex without any cut-off, drop-out, howling, voice level pumping, and annoying echoes.
alc5672 datasheet 52 rev. 0.75 noise suppression: the advanced noise suppression is specifically designed for tablets to benefit users that invoke voice communication applications on these devices. ambient noise pickup is reduced by the advanced microphone array beam-forming which could run in 2- or 3- microphone configurations. the technology further reduces both stationary noise and non-stationary noises, and enhances user experiences in video and voice chats. noise reduction is available on both downstream and upstream signals and is highly effectively against hums, fan-noises, tones, background babbles, and a variety of unwanted interferences. 48khz stereo recording with far-field pickup the vioce dsp provides specific pure 48khz audio recording with ffp technology. it can suppress stationary noise for each channel with 24khz bandwidth. far-field pickup technology is also considered in this mode for long distance audio catch up with high signal to noise ratio. the dual feature sculpture the tablet computer to be a real stereo recording device with stationary noise suppression for long distance range. voice recognition rate enhancement the advanced voice processing could be configured to run in voice recognition rate enhancement mode which would perform beam-forming, acoustic echo cancellation and other processing in a way that helps to improve recognition rates in poor signal- to -noise conditions for the common commercial voice recognition engines. advanced beam-forming the advanced beam-forming algorithm performs voice tracking which could follow the incidence angle of the talkers voice and hence reduces background noise pick -up and reverberations. it also allows for exceptional widened talking angle in handheld mode to accommodate for a wide variety of use r holding positions, and avoids any annoying voice drop-outs and fade-outs.
alc5672 datasheet 53 rev. 0.73 9.18. multi-jack jack detection pin (jd1) the jd1 pin supports up to two ports jack detection. when supports two ports jack detection, the external pull-high voltage is 3.3v. when supports one ports jack detection, the external pull-high voltage is 1.8v. the application schematic as shows below: 0.5 r r 0.5 r cp1 cp2 cp3 3.3v vdd vdd vdd vt1=1.485v vt2=1.95v vt3=2.7v port-1 port-2 r cp2 1.8v vdd vdd vt2=0.9v port-1 mode-0 mode-1 mx -94h: jd1 control name bits read/write reset state description reserved 15:2 r /w 0 h reserved sel_mode_jd1 1:0 r /w 0 h jd 1 mode control 00b: mode -0, two port jack detection 01b: mode -1, one port jack detection others: reserved mx - bf h: jd1 status name bits read/write reset state description sta_jd1_2 (port- 2) 13 r 0 h status of jd1_2 jack detection . read: return status of jack detect select output write: write 0 to clear stick bit sta_jd1_1 (port- 1) 12 r 0 h status of jd1_1 jack detection . read: return status of jack detect select output write: write 0 to clear stick bit
alc5672 datasheet 54 rev. 0.75 10. registers list alc5672 register map as shown as following and accessing unimplemented registers, will return a 0. 10.1. register map table 17 . register map type name description register address reset state reset s/w reset s/w reset & device id mx - 00h 0x0004h hpout headphone output volume & mute/un-mute mx - 02h 0x8888h lout line output volume & mute/un-mute mx - 03h 0x8888h in1 in1 control 1 mx -0ah 0x0001h in1 in1 control 2 mx -0bh 0x0827h in1 in1 control 3 mx -0ch 0x0000h in2 in2 mode and gain boost control mx -0eh 0x0000h inl/inr in l/inr volume control mx -0fh 0x0808h digital gain/volume dacl1/r1 dacl1/r1 digital volume control mx - 19h 0xafafh dacl2/r2-1 dacl2/r2 digital volume control mx -1ah 0xafafh dacl2/r2-2 dacl2/r2 digital mute/un-mute control mx -1bh 0x0000h adc stereo1 adcl/r digital volume & mute/un-mute control mx -1ch 0x2f2fh adc mono adcl/r digital path volume control mx -1dh 0x2f2fh adc adc boost gain for dmic mx -1eh 0x0000h adc stereo2 adcl/r digital volume & mute/un-mute control mx -1fh 0x2f2fh adc adc boost gain for dmic mx - 20h 0x0000h digital mixer adc stereo2 adc digital mixer control mx - 26h 0x7860h adc stereo1 adc digital mixer control mx - 27h 0x7860h adc mono adc digital mixer control mx - 28h 0x7871h adc adc to dac digital mixer control mx -2 9h 0x8080h dac dac stereo digital mixer control mx -2ah 0x5656h dac dac mono digital mixer control mx -2bh 0x5454h dac dac stereo to mono mixer control mx -2ch 0xaaa0h voice dsp voice dsp path control mx -2dh 0x0000h voice dsp voice dsp volume control mx -2eh 0x2f2fh copy mode adc/dac data copy mode control mx -2fh 0x1002h speaker speaker control 1 mx - 31h 0x5f00h input mixer recmixl-1 recmixl gain control mx -3bh 0x0000h recmixl-2 recmixl gain & selection control mx -3ch 0x007fh recmixr-1 recmixr gain control mx -3dh 0x0000h recmixr-2 recmixr gain & selection control mx -3eh 0x007fh output mixer hpomix hpomix gain & selection control mx - 45h 0x600fh outmixl outmixl selection control mx -4fh 0x0073h outmixr outmixr selection control mx - 52h 0x00d3h loutmix loutmix gain & selection control mx - 53h 0xf000h power management management- 1 i2s & dac & adc power control mx - 61h 0x0000h management- 2 digital filter & dsp & spk power control mx - 62h 0x0000h management- 3 vref & mbias & loutmix & hp power control mx - 63h 0x00c0h
alc5672 datasheet 55 rev. 0.75 type name description register address reset state management- 4 micbst & micbias & pll & jd power control mx - 64h 0x0000h management- 5 outmix & recmix power control mx - 65h 0x0000h management- 6 micbias & outvol & hpovol & invol power control mx - 66h 0x0000h pr register pr index pr register index mx -6ah 0x0000h pr data pr register data mx -6ch 0x0000h digital interface i2s1 port ctrl i2s-1 interface control mx - 70h 0x8000h i2s2 port ctrl i2s-2 interface control mx - 71h 0x8000h adc/dac clock adc/dac clock control mx - 73h 0x1114h adc/dac hpf adc/dac hpf control mx - 74h 0x0e00h digital mic digital microphone control mx - 75h 0x1505h digital microphone control mx - 76h 0x0015h tdm tdm interface control mx - 77h 0x0c00h tdm interface control mx - 78h 0x4000h tdm interface control mx - 79h 0x0123h global clock clock dsp clock control mx -7fh 0x1100h clock global clock control mx - 80h 0x0000h pll pll control 1 mx - 81h 0x0000h pll pll control 2 mx - 82h 0x0000h asrc asrc control 1 mx - 83h 0x000 0h asrc asrc control 2 mx - 84h 0x0000h asrc asrc control 3 mx - 85h 0x0000h asrc asrc control 4 mx -8ah 0x0000h asrc asrc control 5 mx -8ch 0x0007h hp amp hp hp output de-pop control 1 mx -8eh 0x0004h hp output de-pop control 2 mx -8fh 0x1100h micbias micbias micbias control mx - 93h 0x0000h jd1 jd1 jd1 control mx - 94h 0x0000h eq adc eq adc eq control 1 mx - ae 0x6000h adc eq adc eq control 2 mx - af 0x0000h dac eq dac eq control 1 mx -b0h 0x6000h dac eq dac eq control 2 mx -b1h 0x0000h eq-parameter dac_l eq (lpf: a1) pr -a4h 0x1c10h eq -parameter dac_l eq (lpf: h0) pr -a5h 0x01f4h eq -parameter dac_r eq (lpf: a1) pr -a6h 0x1c10h eq -parameter dac_r eq (lpf: h0) pr -a7h 0x01f4h eq -parameter dac_l eq (bpf2: a1) pr -aeh 0xc882h eq -parameter dac_l eq (bpf2: a2) pr -afh 0x1c10h eq -parameter dac_l eq (bpf2: h0) pr -b0h 0x01f4h eq -parameter dac_r eq (bpf2: a1) pr -b1h 0xc882h eq -parameter dac_r eq (bpf2: a2) pr -b2h 0x1c10h eq -parameter dac_r eq (bpf2: h0) pr -b3h 0x01f4h eq -parameter dac_l eq (bpf3: a1) pr -b4h 0xe904h eq -parameter dac_l eq (bpf3: a2) pr -b5h 0x1c10h eq -parameter dac_l eq (bpf3: h0) pr -b6h 0x01f4h eq -parameter dac_r eq (bpf3: a1) pr -b7h 0xe904h eq -parameter dac_r eq (bpf3: a2) pr -b8h 0x1c10h
alc5672 datasheet 56 rev. 0.75 type name description register address reset state eq -parameter dac_r eq (bpf3: h0) pr -b9h 0x01f4h eq -parameter dac_l eq (bpf4: a1) pr -bah 0xe904h eq -parameter dac_l eq (bpf4: a2) pr - bbh 0x1c10h eq -parameter dac_l eq (bpf4: h0) pr - bch 0x01f4h eq -parameter dac_r eq (bpf4: a1) pr -bdh 0xe904h eq -parameter dac_r eq (bpf4: a2) pr -beh 0x1c10h eq -parameter dac_r eq (bpf4: h0) pr -bfh 0x01f4h eq -parameter dac_l eq (hpf1: a1) pr -c0h 0x1c10h eq -parameter dac_l eq (hpf1: h0) pr -c1h 0x01f4h eq -parameter dac_r eq (hpf1: a1) pr -c2h 0x1c10h eq -paramet er dac_r eq (hpf1: h0) pr -c3h 0x01f4h eq -parameter dac_l eq (hpf2: a1) pr -c4h 0x2000h eq -parameter dac_l eq (hpf2: a2) pr -c5h 0x0000h eq -parameter dac_l eq (hpf2: h0) pr -c6h 0x1ff1h eq -parameter dac_r eq (hpf2: a1) pr -c7h 0x2000h eq -parameter dac_r eq (hpf2: a2) pr -c8h 0x0000h eq -parameter dac_r eq (hpf2: h0) pr -c9h 0x1ff1h eq -parameter dac_l eq pre-volume control pr -cah 0x0800h eq -parameter dac_r eq pre-volume control pr -cbh 0x0800h eq -parameter dac_l eq post-volume control pr - cc h 0x0800h eq -parameter dac_r eq post-volume control pr -cdh 0x0800h eq -parameter adc eq (lpf: a1) pr -ceh 0x1c10h eq -parameter adc eq (lpf: h0) pr -cfh 0x01f4h eq -parameter adc eq (bpf1: a1) pr -d0h 0xe904h eq -parameter adc eq (bpf1: a2) pr -d1h 0x1c10h eq -parameter adc eq (bpf1: h0) pr -d2h 0x01f4h eq -parameter adc eq (bpf2: a1) pr -d3h 0xe904h eq -parameter adc eq (bpf2: a2) pr -d4h 0x1c10h eq -parameter adc eq (bpf2: h0) pr -d5h 0x01f4h eq -parameter adc eq (bpf3: a1) pr -d6h 0xe904h eq -parameter adc eq (bpf3: a2) pr -d7h 0x1c10h eq -parameter adc eq (bpf3: h0) pr -d8h 0x01f4h eq -parameter adc eq (bpf4: a1) pr -d9h 0xe904h eq -parameter adc eq (bpf4: a2) pr -dah 0x1c10h eq -parameter adc eq (bpf4: h0) pr -dbh 0x01f4h eq -parameter adc eq (hpf1: a1) pr -dch 0x1c10h eq -parameter adc eq (hpf1: h0) pr -ddh 0x01f4h eq -parameter adc eq pre-volume control pr -e1h 0x0800h eq -parameter adc eq post-volume control pr -e2h 0x0800h eq -parameter dac_l biquad eq (bpf1: h0- 1) pr -e5h 0x000 0h eq -parameter dac_l biquad eq (bpf1: h0- 2) pr -e6h 0x0000h eq -parameter dac_l biquad eq (bpf1: b1- 1) pr -e7h 0x0000h eq -parameter dac_l biquad eq (bpf1: b1- 2) pr -e8h 0x0000h eq -parameter dac_l biquad eq (bpf1: b2- 1) pr -e9h 0x0000h eq -paramet er dac_l biquad eq (bpf1: b2- 2) pr -eah 0x0000h eq -parameter dac_l biquad eq (bpf1: a1- 1) pr -ebh 0x0000h eq -parameter dac_l biquad eq (bpf1: a1- 2) pr -ech 0x0000h eq -parameter dac_l biquad eq (bpf1: a2- 1) pr -edh 0x0000h eq -parameter dac_l biquad eq (bpf1: a2- 2) pr - eeh 0x0000h eq -parameter dac_r biquad eq (bpf1: h0- 1) pr -efh 0x0000h eq -parameter dac_r biquad eq (bpf1: h0- 2) pr -f0h 0x0000h
alc5672 datasheet 57 rev. 0.75 type name description register address reset state eq -parameter dac_r biquad eq (bpf1: b1- 1) pr -f1h 0x0000h eq -parameter dac_r biquad eq (bpf1: b1- 2) pr -f2h 0x0000h eq -parameter dac_r biquad eq (bpf1: b2- 1) pr -f3h 0x0000h eq -parameter dac_r biquad eq (bpf1: b2- 2) pr -f4h 0x0000h eq -parameter dac_r biquad eq (bpf1: a1- 1) pr -f5h 0x0000h eq -parameter dac_r biquad eq (bpf1: a1- 2) pr -f6h 0x0000h eq -parameter dac_r biquad eq (bpf1: a2- 1) pr -f7h 0x0000h eq -parameter dac_r biquad eq (bpf1: a2- 2) pr -f8h 0x0000h drc/agc drc/agc drc/agc control 1 mx -b2h 0x0000h drc/agc drc/agc control 2 mx -b3h 0x001fh drc/agc drc/agc control 3 mx -b4h 0x2206 h drc/agc drc/agc control 4 mx -b5h 0x1f00h drc/agc drc/agc control 5 mx -b6h 0x0000h drc/agc drc/agc control 6 mx -b7h 0x0000h jack detection jd jack detection control mx - bbh 0x0000h jd jack detection control mx -f8h 0x0000h jd jack detection control mx -f9h 0x0000h irq irq irq control 1 mx -bdh 0x0000h irq irq control 2 mx -beh 0x0000h irq irq control 3 mx -bfh 0x0000h gpio gpio gpio control 1 mx -c0h 0x0000h gpio gpio control 2 mx -c2h 0x0000h gpio gpio control 3 mx -c3h 0x0000h sounzreal tm post-processin g bassback bassback control mx -cfh 0x0013h trutreble trutreble control 1 mx -d0h 0x0680h trutreble trutreble control 2 mx -d1h 0x1c17h wind filter stereo1 stereo1 adc wind filter control 1 mx -d3h 0xaa20h stereo1 stereo1 adc wind filter control 2 mx -d4h 0x0000h mono mono adc wind filter control 1 mx -ech 0xaa20h mono mono adc wind filter control 2 mx -edh 0x0000h stereo2 stereo2 adc wind filter control 1 mx -eeh 0xaa20h stereo2 stereo2 adc wind filter control 2 mx-efh 0x0000h svol & zcd svol & zcd soft volume and zcd control 1 mx -d9h 0x0809h soft volume and zcd control 2 mx -dah 0x0000h inline command inline command control 1 mx -dbh 0x0001h inline command control 2 mx -dch 0x0049h inline command control 3 mx -ddh 0x0003h voice dsp voice dsp control 1 mx -e0h 0x0000h voice dsp control 2 mx -e1h 0x0000h voice dsp control 3 mx -e2h 0x0000h voice dsp control 4 mx -e3h 0x0000h voice dsp control 5 mx -e4h 0x0000h voice dsp control 6 mx -e5h 0x0000h general control general control 1 mx -fah 0x801 0h general control 2 mx -fbh 0x0033h adc/dac reset control pr - 3d 0x2808h vendor id id vendor id mx -feh 0x10ech
alc5672 datasheet 58 rev. 0.75 10.2. mx -00h: s/w reset & device id default: 0004 h table 18 . mx -00h: s/w res et port name bits read/write reset state description reserved 15: 3 r 0 h reserved device_id 2:1 r 2 h alc5672 reserved 0 r 0h reserved note: writes to this register will reset all registers to their default values. 10.3. mx -02h: headphone output control default: 8888 h table 19 . mx -02h: headphone output control name bits read/write reset state description mu_ hpo_l 15 r/w 1 h mute control for left headphone output port (hpol) 0 b : un -mute 1 b : mute reserved 14 r 0 h reserved vol_hpol 13 :8 r/w 8 h lef t headphone channel volume control (hpovoll) ? 00h: +12db 08h: 0db 27h: -46.5db, with 1.5db/step m u_ hpo_r 7 r/w 1 h mute control right headphone output port (hpor) 0 b : un -mute 1b: mute reserved 6 r 0 h reserved vol_ hp or 5 :0 r/w 8 h right headphone channel volume control (hpovolr) ? 00h: +12db 08h: 0db 27h: -46.5db, with 1.5db/step
alc5672 datasheet 59 rev. 0.75 ? volume table dec hex boost gain dec hex boost gain dec hex boost gain 0 0 12 16 10 - 12 32 20 - 36 1 1 10.5 17 11 -13.5 33 21 -37.5 2 2 9 18 12 - 15 34 22 -39 3 3 7.5 19 13 -16.5 35 23 -40.5 4 4 6 20 14 - 18 36 24 - 42 5 5 4.5 21 15 -19.5 37 25 -43.5 6 6 3 22 16 - 21 38 26 - 45 7 7 1.5 23 17 -22.5 39 27 -46.5 8 8 0 24 18 - 24 9 9 -1.5 25 19 -25.5 10 a -3 26 1a - 27 11 b -4.5 27 1b -28.5 12 c -6 28 1c - 30 13 d -7.5 29 1d -31.5 14 e -9 30 1e - 33 15 f -10.5 31 1f -34.5 10.4. mx -03h: line output control default: 8888 h table 20. mx -03 h: line output control name bits read/write reset state description mu_lout_l 15 r/w 1 h mute control for left line output port(lout l) 0 b : un -mute 1b: mute en_dfo1 14 r/w 0 h lout differential mode control 0 b : disable (single-ended mode) 1b: enable (differential mode) vol_outl 13 :8 r/w 08 h left output volume control (outvoll) ? 00h: +12db 08h: 0 db 27h: -46.5db, with 1.5db/step mu_lout_r 7 r/w 1 h mute control for right line output port (loutr) 0 b : un -mute 1b: mute reserved 6 r 0 h reserved
alc5672 datasheet 60 rev. 0.75 name bits read/write reset state description vol_outr 5 :0 r/w 08 h right output volume control ? 00h: +12db 08h: 0db 27h: -46.5db, with 1.5db/step ? volume table dec hex boost gain dec hex boost gain dec hex boost gain 0 0 12 16 10 - 12 32 20 - 36 1 1 10.5 17 11 -13.5 33 21 -37.5 2 2 9 18 12 - 15 34 22 - 39 3 3 7.5 19 13 -16.5 35 23 -40.5 4 4 6 20 14 - 18 36 24 - 42 5 5 4.5 21 15 -19.5 37 25 -43.5 6 6 3 22 16 - 21 38 26 - 45 7 7 1.5 23 17 -22.5 39 27 -46.5 8 8 0 24 18 - 24 9 9 -1.5 25 19 -25.5 10 a -3 26 1a - 27 11 b -4.5 27 1b -28.5 12 c -6 28 1c - 30 13 d -7.5 29 1d -31.5 14 e -9 30 1e - 33 15 f -10.5 31 1f -34.5
alc5672 datasheet 61 rev. 0.75 10.5. mx -0ah: in1 port control - 1 default: 0001 h table 21. mx -0d h: in1 input control - 1 name bits read/write reset state description sel_bst1 15:12 r /w 0 h in1 boost control (bst1) 0000b: bypass 0001b: +20db 0010b: +24db 0011b: +30db 010 0b: +35db 0101b: +40db 0110b: +44db 0111b: +50db 1000b: +52db others : reserved reserved 11:3 r/w 0h reserved en_bst1 2 r/w 0h in1 port enable control 0b: disable 1b: enable reserved 1:0 r/w 1h reserved 10.6. mx -0bh: in1 port control - 2 default : 0827 h table 22. mx -0b h: in1 input control - 2 name bits read/write reset state description reserved 15:13 r 0 h reserved manual_tri_in1 12 r/w 0h manual trigger for in1 port 0b: low trigger 1b: high trigger capless_gat_en 11 r/w 1h capless power gating with in1 control 0b: register control 1b: auto mode reserved 10:8 r/w 0h reserved reg_mode 7 r/w 1h in1 port mode control 0b: auto mode 1b: manual mode reserved 6:0 r/w 27h reserved
alc5672 datasheet 62 rev. 0.75 10.7. mx -0ch: in1 port control - 3 default: 0000 h table 23. mx -0c h: in1 input control - 3 name bits read/write reset state description reserved 15:3 r 0 h reserved in1_result 2:0 r 0h in1 port final status 001b: type1 010b: type2 100b: type3 10.8. mx -0eh: in2 input control default: 0000 h table 24. mx -0e h: in 2 input control name bits read/write reset state description sel_bst2 15:12 r /w 0 h in2 boost control (bst2) 0000b: bypass 0001b: +20db 0010b: +24db 0011b: +30db 0100b: +35db 0101b: +40db 0110b: +44db 0111b: +50db 1000b: +52db others : reserved reserved 11:8 r /w 0h reserved en_in2_df 7 r/w 0 h in2 input mode control 0b: single ended mode 1b: differential mode reserved 6:0 r 0h reserved
alc5672 datasheet 63 rev. 0.75 10.9. mx -0fh: in l & inr volume control default: 0808 h table 25. mx -0f h: in l & inr volume control name bits read/write reset state description reserved 15:13 r 0h reserved vol_inl 12:8 r /w 8 h inl channel volume control ? 00h: +12db 08h: 0db 1fh: -34.5db, with 1.5db/step reserved 7:5 r 0h reserved vol_inr 4:0 r /w 8 h inr channel volume contro l ? 00h: +12db 08h: 0db 1fh: -34.5db, with 1.5db/step ? volume table: dec hex boost gain dec hex boost gain 0 0 12 16 10 - 12 1 1 10.5 17 11 -13.5 2 2 9 18 12 - 15 3 3 7.5 19 13 -16.5 4 4 6 20 14 - 18 5 5 4.5 21 15 -19.5 6 6 3 22 16 - 21 7 7 1.5 23 17 -22.5 8 8 0 24 18 - 24 9 9 -1.5 25 19 -25.5 10 a -3 26 1a - 27 11 b -4.5 27 1b -28.5 12 c -6 28 1c - 30 13 d -7.5 29 1d -31.5 14 e -9 30 1e - 33 15 f -10.5 31 1f -34.5
alc5672 datasheet 64 rev. 0.75 10.10. mx -19h: dacl1/r1 digital volume default: afaf h table 26 . mx -19 h: da cl1/r1 digital volume name bits read/write reset state description vol_dac 1_l 15 :8 r/w af h dac 1 left channel digital volume ? 00h: -65.625db afh: 0db, with 0.375db/step vol_dac 1_r 7:0 r/w af h dac 1 right channel digital volume ? 00h: -65.625db afh: 0db, with 0.375db/step 10.11. mx -1ah: dacl 2 /r 2 digital volume default: afaf h table 27 . mx -1a h: da c l2 /r 2 digital volume name bits read/write reset state description vol_dac2 _l 15 :8 r/w af h dac 2 left channel digital volume ? 00h: -65.625db afh: 0db, with 0.37 5db/step vol_dac2 _r 7:0 r/w af h dac 2 right channel digital volume ? 00h: -65.625db afh: 0db, with 0.375db/step ? volume table: dec hex boost gain dec hex boost gain dec hex boost gain dec hex boost gain dec hex boost gain 0 0 -65.625 53 35 -45.75 106 6a -25.875 159 9f -6 212 d4 1 1 -65.25 54 36 -45.375 107 6b -25.5 160 a0 -5.625 213 d5 2 2 -64.875 55 37 - 45 108 6c -25.125 161 a1 -5.25 214 d6 3 3 -64.5 56 38 -44.625 109 6d -24.75 162 a2 -4.875 215 d7 4 4 -64.125 57 39 -44.25 110 6e -24.375 163 a3 -4.5 216 d8 5 5 -63.75 58 3a -43.875 111 6f - 24 164 a4 -4.125 217 d9 6 6 -63.375 59 3b -43.5 112 70 -23.625 165 a5 -3.75 218 da 7 7 - 63 60 3c -43.125 113 71 -23.25 166 a6 -3.375 219 db
alc5672 datasheet 65 rev. 0.75 8 8 -62.625 61 3d -42.75 114 72 -22.875 167 a7 -3 220 dc 9 9 -62.25 62 3e -42.375 115 73 -22.5 168 a8 -2.625 221 dd 10 a -61.875 63 3f - 42 116 74 -22.125 169 a9 -2.25 222 de 11 b -61.5 64 40 -41.625 117 75 -21.75 170 aa -1.875 223 df 12 c -61.125 65 41 -41.25 118 76 -21.375 171 ab -1.5 224 e0 13 d -60.75 66 42 -40.875 119 77 - 21 172 ac -1.125 225 e1 14 e -60.375 67 43 -40.5 120 78 -20.625 173 ad -0.75 226 e2 15 f - 60 68 44 -40.125 121 79 -20.25 174 ae -0.375 227 e3 16 10 -59.625 69 45 -39.75 122 7a -19.875 175 af 0 228 e4 17 11 -59.25 70 46 -39.375 123 7b -19.5 176 b0 229 e5 18 12 -58.875 71 47 - 39 124 7c -19.125 177 b1 230 e6 19 13 -58.5 72 48 -38.625 125 7d -18.75 178 b2 231 e7 20 14 -58.125 73 49 -38.25 126 7e -18.375 179 b3 232 e8 21 15 -57.75 74 4a -37.875 127 7f - 18 180 b4 233 e9 22 16 -57.375 75 4b -37.5 128 80 -17.625 181 b5 234 ea 23 17 - 57 76 4c -37.125 129 81 -17.25 182 b6 235 eb 24 18 -56.625 77 4d -36.75 130 82 -16.875 183 b7 236 ec 25 19 -56.25 78 4e -36.375 131 83 -16.5 184 b8 237 ed 26 1a -55.875 79 4f - 36 1 32 84 -16.125 185 b9 238 ee 27 1b -55.5 80 50 -35.625 133 85 -15.75 186 ba 239 ef 28 1c -55.125 81 51 -35.25 134 86 -15.375 187 bb 240 f0 29 1d -54.75 82 52 -34.875 135 87 - 15 188 bc 241 f1 30 1e -54.375 83 53 -34.5 136 88 -14.625 189 bd 242 f2 31 1f - 54 84 54 -34.125 137 89 -14.25 190 be 243 f3 32 20 -53.625 85 55 -33.75 138 8a -13.875 191 bf 244 f4 33 21 -53.25 86 56 -33.375 139 8b -13.5 192 c0 245 f5 34 22 -52.875 87 57 - 33 140 8c -13.125 193 c1 246 f6 35 23 -52.5 88 58 -32.625 141 8d -12.75 194 c2 247 f7 36 24 -52.125 89 59 -32.25 142 8e -12.375 195 c3 248 f8 37 25 -51.75 90 5a -31.875 143 8f - 12 196 c4 249 f9 38 26 -51.375 91 5b -31.5 144 90 -11.625 197 c5 250 fa 39 27 - 51 92 5c -31.125 145 91 -11.25 198 c6 251 fb 40 28 -50.625 93 5d -30.75 146 92 -10.875 199 c7 252 fc 41 29 -50.25 94 5e -30.375 147 93 -10.5 200 c8 253 fd 42 2a -49.875 95 5f - 30 148 94 -10.125 201 c9 254 fe 43 2b -49.5 96 60 -29.625 149 95 -9.75 202 ca 255 ff
alc5672 datasheet 66 rev. 0.75 44 2c -49.125 97 61 -29.25 150 96 -9.375 203 cb 45 2d -48.75 98 62 -28.875 151 97 -9 204 cc 46 2e -48.375 99 63 -28.5 152 98 -8.625 205 cd 47 2f - 48 100 64 -28.125 153 99 -8.25 206 ce 48 30 -47.625 101 65 -27.75 154 9a -7.875 207 cf 49 31 -47.25 102 66 - 27 .375 155 9b -7.5 208 d0 50 32 -46.875 103 67 - 27 156 9c -7.125 209 d1 51 33 -46.5 104 68 -26.625 157 9d -6.75 210 d2 52 34 -46.125 105 69 -26.25 158 9e -6.375 211 d3 10.12. mx -1bh: dacl2/r2 mute/un-mute control default: 000 0 h table 28 . mx -1b h: dacl2/r2 mute/un-mute control name bits read/write reset state description reserved 15:14 r 0h reserved mu_dac2_l 13 r/w 0h mute control for left dac2 volume 0b: un -mute 1b: mute mu_dac2_r 12 r/w 0h mute control for right dac2 volume 0b: un -mute 1b: mute reserved 11: 7 r 0h reserved sel_dacl2 6:4 r/w 1h select dacl2 data source 000b: if1_dac2_l 001b: if2_dac_l 010b: reserved 011b: txdc_dac_l others: reserved reserved 3 r 0h reserved
alc5672 datasheet 67 rev. 0.75 sel_dacr2 2:0 r/w 1h select dacr2 data source 000b: if1_dac2_r 001b: if2_dac_r 010b: reserved 011b: txdc_dac_r 100b: txdp_dac_l others: reserved 10.13. mx -1ch: stereo1 adc digital volume control default: 2f2f h table 29 . mx - 1c h: stereo1 adc digital volume control name bits read/write reset state description mu_adc_vol_l 15 r/w 0h mute control for stereo1 adc left volume channel 0b: un -mute 1b: mute ad_gain_l 14:8 r/w 2fh stereo1 adc left channel volume control 00h: -17.625db 2fh: 0db 7fh: +30db, with 0. 375db/step mu_adc_vol _r 7 r/w 0h mute control for stereo1 adc right volume channel 0b: un -mute 1b: mute ad_gain_r 6:0 r/w 2fh stereo1 adc right channel volume control 00h: -17.625db 2fh: 0db 7fh: +30db, with 0.375db/step
alc5672 datasheet 68 rev. 0.75 10.14. mx -1dh: mono adc digital volume control default: 2f2f h table 30. mx - 1d h: mono adc digital volume control name bits read/write reset state description reserved 15 r 0h reserved mono_ad_gain_l 14:8 r/w 2fh mono adc left channel volume control ? 00h: -17.625db 2f h: 0db 7fh: +30db, with 0.375db/step reserved 7 r 0h reserved mono_ad_gain_r 6:0 r/w 2fh mono adc right channel volume control ? 00h: -17.625db 2fh: 0db 7fh: +30db, with 0.375db/step ? volume table: dec hex boost gain dec hex boost gain dec h ex boost gain dec hex boost gain dec hex boost gain 0 0 -17.625 26 1a -7.875 52 34 1.875 78 4e 11.625 104 68 21.375 1 1 -17.25 27 1b -7.5 53 35 2.25 79 4f 12 105 69 21.75 2 2 -16.875 28 1c -7.125 54 36 2.625 80 50 12.375 106 6a 22.125 3 3 -16.5 29 1d -6.75 55 37 3 81 51 12.75 107 6b 22.5 4 4 -16.125 30 1e -6.375 56 38 3.375 82 52 13.125 108 6c 22.875 5 5 -15.75 31 1f -6 57 39 3.75 83 53 13.5 109 6d 23.25 6 6 -15.375 32 20 -5.625 58 3a 4.125 84 54 13.875 110 6e 23.625 7 7 - 15 33 21 -5.25 59 3b 4.5 85 55 14.25 111 6f 24 8 8 -14.625 34 22 -4.875 60 3c 4.875 86 56 14.625 112 70 24.375 9 9 -14.25 35 23 -4.5 61 3d 5.25 87 57 15 113 71 24.75 10 a -13.875 36 24 -4.125 62 3e 5.625 88 58 15.375 114 72 25.125 11 b -13.5 37 25 -3.75 63 3f 6 89 59 15.75 115 73 25.5 12 c -13.125 38 26 -3.375 64 40 6.375 90 5a 16.125 116 74 25.875 13 d -12.75 39 27 -3 65 41 6.75 91 5b 16.5 117 75 26.25 14 e -12.375 40 28 -2.625 66 42 7.125 92 5c 16.875 118 76 26.625 15 f - 12 41 29 -2.25 67 43 7.5 93 5d 17.25 119 77 27 16 10 -11.625 42 2a -1.875 68 44 7.875 94 5e 17.625 120 78 27.375 17 11 -11.25 43 2b -1.5 69 45 8.25 95 5f 18 121 79 27.75 18 12 -10.875 44 2c -1.125 70 46 8.625 96 60 18.375 122 7a 28.125 19 13 -10.5 45 2d -0.75 71 47 9 97 61 18.75 123 7b 28.5 20 14 -10.125 46 2e -0.375 72 48 9.375 98 62 19.125 124 7c 28.875 21 15 -9.75 47 2f 0 73 49 9.75 99 63 19.5 125 7d 29.25
alc5672 datasheet 69 rev. 0.75 22 16 -9.375 48 30 0.375 74 4a 10.125 100 64 19.875 126 7e 29.625 23 17 -9 49 31 0.75 75 4b 10.5 101 65 20.25 127 7f 30 24 18 -8.625 50 32 1.125 76 4c 10.875 102 66 20.625 25 19 -8.25 51 33 1.5 77 4d 11.25 103 67 21 10.15. mx -1eh: adc digital boost gain control default: 0000 h table 31. mx - 1e h: adc digital boost gain control name bits read/write reset state description stereo1_ad_boost_ gain_l 15:14 r/w 0h stereo1 adc left channel digital boost gain 00b: 0db 01b: 12db 10b: 24db 11b: 36db stereo1_ad_boost_ gain_r 13:12 r/w 0h stereo1 adc right channel digital boost gain 00b: 0db 01b: 12db 10b: 24db 11b: 36db stereo1_ad_comp_ gain 11:10 r/w 0h stereo1 adc compensation gain 00b: 0db 01b: 1db 10b: 2db 11b: 3db stereo2_ad_boost_ gain_l 9:8 r/w 0h stereo2 adc left channel digital boost gain 00b: 0db 01b: 12db 10b: 24db 11b: 36db stereo2_ad_boost_ gain_r 7:6 r/w 0h stereo2 adc right channel digital boost gain 00b: 0db 01b: 12db 10b: 24db 11b: 36db
alc5672 datasheet 70 rev. 0.75 stereo2_ad_comp_ gain 5:4 r/w 0h stereo2 adc compensation gain 00b: 0db 01b: 1db 10b: 2db 11b: 3db reserved 3:0 r/w 0h reserved 10.16. mx -1fh: stereo2 adc digital volume control default: 2f2f h table 32. mx -1f h: stereo2 adc digital volume control name bits read/write reset state description mu_adc2_vol_l 15 r/w 0h mute control for stereo2 adc left volume channel 0b: un -mute 1b: mute ad2_gain_l 14:8 r/w 2fh stereo2 adc left channel volume control 00h: -17.625db 2fh: 0db 7fh: +30db, with 0.375db/step mu_adc2_vol_r 7 r/w 0h mute control for stereo2 adc right volume channel 0b: un -mute 1b: mute ad2_gain_r 6:0 r/w 2fh stereo2 adc right channel volume control 00h: -17.625db 2fh: 0db 7fh: +30db, with 0.375db/step
alc5672 datasheet 71 rev. 0.75 10.17. mx -20h: mono adc digital boost gain control default: 0000 h table 33. mx - 20 h: mono adc digital boost gain control name bits read/write reset state description mono_ad_boost_ga in_l 15:14 r/w 0h mono adc left channel digital boost gain 00b: 0db 01b: 12db 10b: 24db 11b: 36db mono_ad_boost_ga in_r 13:12 r/w 0h mono adc right channel digital boost gain 00b: 0db 01b: 12db 10b: 24db 11b: 36db mono_ad_comp_ga in 11:10 r/w 0h mono adc compensation gain 00b: 0db 01b: 1db 10b: 2db 11b: 3db reserved 9:0 r 0h reserved 10.18. mx -26h: stereo2 adc digital mixer control default: 7860 h table 34. mx -26 h: stereo2 adc digital mixer control name bits read/write reset state description sel_stereo2_lr_mix 15 r/w 0h mixing control for stereo2 adc left channel 0b: l 1b: l+r mu_stereo2_adcl1 14 r/w 1h mute source1 to stereo2 adc left channel 0b:unmute 1b:mute mu_stereo2_adcl2 13 r/w 1h mute source2 to stereo2 adc left channel 0b:unmute 1b:mute sel_stereo2_adc1 12 r /w 1 h select stereo2 adc l/r channel source 1 0b: dac_mixl / dac_mixr 1b: adc1
alc5672 datasheet 72 rev. 0.75 sel_stereo2_adc2 11 r /w 1 h select stereo2 adc l/r channel source 2 0b: dac_mixl / dac_mixr 1b: dmic1/dmic2/dmic3 reserved 10 r/w 0h reserved sel_stereo2_dmic 9:8 r/w 0h select stereo2 dmic source 00b: dmic1 01b: dmic2 10b: dmic3 11b: reserved reserved 7 r 0h reserved mu_stereo2_adcr1 6 r/w 1h mute source1 to stereo2 adc right channel 0b:unmute 1b:mute mu_stereo2_adcr2 5 r/w 1h mute source2 to stereo2 adc right channel 0b:unmute 1b:mute reserved 4:0 r 0h reserved 10.19. mx -27h: stereo1 adc digital mixer control default: 7860 h table 35. mx - 27 h: stereo1 adc digital mixer control name bits read/write reset state description reserved 15 r 0h reserved mu_stereo1_adcl1 14 r/w 1h mute source 1 to stereo1 adc left channel 0b:unmute 1b:mute mu_stereo1_adcl2 13 r/w 1h mute source 2 to stereo1 adc left channel 0b:unmute 1b:mute sel_stereo1_adc1 12 r /w 1 h select stereo1 adc l/r channel source 1 0b: dac_mixl / dac_mixr 1b: adc1 sel_stereo1_adc2 11 r /w 1 h select stereo1 adc l/r channel source 2 0b: dac_mixl / dac_mixr 1b: dmic1/dmic2/dmic3 reserved 10 r/w 0h reserved sel_stereo1_dmic 9:8 r/w 0h select stereo1 dmic source 00b: dmic1 01 b: dmic2 10b: dmic3 11b: reserved reserved 7 r 0h reserved mu_stereo1_adcr1 6 r/w 1h mute source 1 to stereo1 adc right channel 0b:unmute 1b:mute mu_stereo1_adcr2 5 r/w 1h mute source 2 to stereo1 adc right channel 0b:unmute 1b:mute
alc5672 datasheet 73 rev. 0.75 reserved 4: 0 r 0h reserved 10.20. mx -28h: mono adc digital mixer control default: 7871 h table 36. mx - 28 h: mono adc digital mixer control name bits read/write reset state description reserved 15 r 0h reserved mu_mono_adcl1 14 r/w 1h mute source 1 to mono adc left channel 0b:unmute 1b:mute mu_mono_adcl2 13 r/w 1h mute source 2 to mono adc left channel 0b:unmute 1b:mute sel_mono_adcl1 12 r /w 1 h select mono adc left channel source 1 0b: mono_dac_mixer_l 1b: adc1 sel_mono_adcl2 11 r /w 1 h select mono adc le ft channel source 2 0b: mono_dac_mixer_l 1b: dmic1_l or dmic2_l or dmic3_l reserved 10 r/w 0h reserved sel_mono_dmic_l 9:8 r/w 0h select mono left channel dmic source 00b: dmic1_l 01b: dmic2_l 10b: dmic3_l 11b: reserved reserved 7 r 0h reserved mu_mono_adcr1 6 r/w 1h mute source 1 to mono adc right channel 0b:unmute 1b:mute mu_mono_adcr2 5 r/w 1h mute source 2 to mono adc right channel 0b:unmute 1b:mute sel_mono_adcr1 4 r /w 1 h select mono adc right channel source 1 0b: mono_dac_mixer_r 1b: adc2 sel_mono_adcr2 3 r /w 0 h select mono adc right channel source 2 0b: mono_dac_mixer_r 1b: dmic1_r or dmic2_r or dmic3_r reserved 2 r/w 0h reserved sel_mono_dmic_r 1:0 r/w 1h select mono right channel dmic source 00b: dmic1_r 01b: dmic2_ r 10b: dmic3_r 11b: reserved
alc5672 datasheet 74 rev. 0.75 10.21. mx -29h: stereo adc to dac digital mixer control default: 8080 h table 37. mx - 29 h: stereo adc to dac digital mixer control name bits read/write reset state description mu_stereo1_adc_mix er_l 15 r/w 1h mute stereo1 adc to dac1 left channel 0b:unmute 1b:mute mu_dac1_l 14 r /w 0h mute if1 dac left channel 0b:unmute 1b:mute reserved 13:12 r 0h reserved sel_dacr1 11:10 r/w 0h dacr1 source selection 00b: if1_dac1_r 01b: if2_dac_r 10b: reserved 11b: reserved sel_dacl1 9:8 r/w 0h dacl1 source selection 00b: if1_dac1_l 01b: if2_dac_l 10b: reserved 11b: reserved mu_stereo1_adc_mix er_r 7 r/w 1h mute stereo1 adc to dac1 right channel 0b:unmute 1b:mute mu_dac1_r 6 r /w 0h mute if1 dac right channel 0b:unmute 1 b:mute reserved 5:0 r 0h reserved 10.22. mx -2ah: stereo dac digital mixer control default: 5656 h table 38. mx - 2a h: stereo dac digital mixer control name bits read/write reset state description reserved 15 r 0h reserved mu_stereo_dacl1_mix l 14 r/w 1h mute stereo dac1 left channel 0b:unmute 1b:mute gain_dacl1_to_stereo _l 13 r/w 0h gain control for dacl1 to stereo left mixer 0 b : 0db 1 b : - 6db mu_stereo_dacl2_mix l 12 r/w 1h mute stereo dac2 left channel 0b:unmute 1b:mute gain_dacl2_to_stereo _l 11 r/w 0h gain control for dacl2 to stereo left mixer 0 b : 0db 1 b : - 6db
alc5672 datasheet 75 rev. 0.75 name bits read/write reset state description reserved 10 r/w 1h reserved mu_ stereo_dacr1_mi xl 9 r/w 1h mute stereo dac1 right channel to left mixer 0b:unmute 1b:mute gain_dacr1_to_stereo _l 8 r/w 0h gain control for dacr1 to stereo left mixer 0 b : 0db 1 b : - 6db reserved 7 r 0h reserved mu_stereo_dacr1_mi xr 6 r/w 1h mute stereo dac1 right channel 0b:unmute 1b:mute gain_dacr1_to_stereo _r 5 r/w 0h gain control for dacr1 to stereo right mixer 0 b : 0db 1 b : - 6db mu_stereo_dacr2_mi xr 4 r/w 1h mute stereo dac2 right channel 0b:unmute 1b:mute gain_dacr2_to_stereo _r 3 r/w 0h gain control for dacr2 to stereo right mixer 0 b : 0db 1 b : - 6db reserved 2 r/w 1h reserved mu_ stereo_dacl1_mix r 1 r/w 1h mute stereo dac1 le ft channel to right mixer 0b:unmute 1b:mute gain_dacl1_to_stereo _r 0 r/w 0h gain control for dacl1 to stereo right mixer 0 b : 0db 1 b : - 6db 10.23. mx -2bh: mono dac digital mixer control default: 5454 h table 39 . mx - 2b h: mono dac digital mixer control name bits read/write reset state description reserved 15 r 0h reserved mu_mono_dacl1_mix l 14 r/w 1h mute dac1 left channel to mono dac left mixer 0b:unmute 1b:mute gain_mono_l_dacl1 13 r/w 0h gain control for dac1 left channel to mono dac left mixer 0 b : 0db 1 b : - 6db mu_mono_dacl2_mix l 12 r/w 1h mute dac2 left channel to mono dac left mixer 0b:unmute 1b:mute gain_mono_l_dacl2 11 r/w 0h gain control for dac2 left channel to mono dac left mixer 0 b : 0db 1 b : - 6db
alc5672 datasheet 76 rev. 0.75 name bits read/write reset state description mu_mono_dacr2_mix l 10 r/w 1h mute dac2 right channel to mono dac left mixer 0b:unmute 1b:mute gain_mono_l_dacr2 9 r/w 0h gain control for dac2 right channel to mono dac left mixer 0 b : 0db 1 b : - 6db reserved 8:7 r 0h reserved mu_mono_dacr1_mix r 6 r/w 1h mute dac1 right channel to mono dac right mixer 0b:unmute 1b:mute gain_mono_r_dacr1 5 r/w 0h gain control for dac1 right channel to mono dac right mixer 0 b : 0db 1 b : - 6db mu_mono_dacr2_mix r 4 r/w 1h mute dac2 right channel to mono dac right mixer 0b:unmute 1b:mute gain_mono_r_dacr2 3 r/w 0h gain control for dac2 right channel to mono dac right mixer 0 b : 0db 1 b : - 6db mu_mono_dacl2_mix r 2 r/w 1h mute dac2 left channel to mono dac right mixer 0b:unmute 1b:mute gain_mono_r_dacl2 1 r/w 0h gain control for dac2 left channel to mono dac right mixer 0 b : 0db 1 b : - 6db reserved 0 r 0h reserved 10.24. mx -2ch: dac digital mixer control default: aa a 0 h table 40. mx - 2c h: dac digital mixer control name bits read/write reset state description mu_stereomixl_to_da cmixl 15 r/w 1h mu te stereo_dac_mixer_l to dac_mixl 0b:unmute 1b:mute gain_stereomixl_to_d acmixl 14 r/w 0h gain control for stereo_dac_mixer_l to dac_mixl 0 b : 0db 1 b : - 6db mu_dacl2_to_dacmix l 13 r/w 1h mute dacl2 to dac_mixl 0b:unmute 1b:mute gain_dacl2_to_dacmi xl 12 r/w 0h gain control for dacl2 to dac_mixl 0 b : 0db 1 b : - 6db
alc5672 datasheet 77 rev. 0.75 name bits read/write reset state description mu_stereomixr_to_da cmixr 11 r/w 1h mute stereo_dac_mixer_r to dac_mixr 0b:unmute 1b:mute gain_stereomixr_to_d acmixr 10 r/w 0h gain control for stereo_dac_mixer_r to dac_mixr 0 b : 0db 1 b : - 6db mu_dacr2_to_dacmix r 9 r/w 1h mute dacr2 to dac_mixr 0b:unmute 1b:mute gain_dacr2_to_dacmi xr 8 r/w 0h gain control for dacr2 to dac_mixr 0 b : 0db 1 b : - 6db mu_dacr2_to_dacmix l 7 r/w 1h mute dacr2 to dac_mixl 0b:unmute 1b:mute gain_dacr2_to_dacmi xl 6 r/w 0h gain control for dacr2 to dac_mixl 0 b : 0db 1 b : - 6db mu_dacl2_to_dacmix r 5 r/w 1h mute dacl2 to dac_mixr 0b:unmute 1b:mute gain_dacl2_to_dacmi xr 4 r/w 0h gain control for dacl2 to dac_mixr 0 b : 0db 1 b : - 6db reserved 3:0 r 0h reserved 10.25. mx -2dh: voice dsp path control 1 default: 0000 h table 41. mx - 2d h: voice dsp path control 1 name bits read/write reset state description sel_rxdp_in 15:13 r/w 0h rxdp input selection 000b: if2_dac_l/r 001b: if1_dac2_l/r 010b: stereo1_adc _mixer_l/r 011b: stereo2_adc_mixer_l/r 100b: mono_adc_mixer_l 101b: mono_adc_mixer_r 110b: dacl1/r1 (after eq/alc/ sounzreal tm ) 111b: reserved sel_src_to_rxdp 12:11 r/w 0h select src to rxdp 00b: bypass 01b: /2 10b: /3 11b: reserved reserved 10 r 0h reserved
alc5672 datasheet 78 rev. 0.75 name bits read/write reset state description sel_txdp_data 9:8 r/w 0h txdp output data swap 00b: l/r 01b: r/l 10b: l/l 11b: r/r sel_txdc_data 7:6 r/w 0h txdc output data swap 00b: l/r 01b: r/l 10b: l/l 11b: r/r sel_src_to_txdp 5:4 r/w 0h select src to txdp 00b: bypass ( stereo signal) 01b: /2 (mono signal) 10b: /3 (mono signal) 11b: reserved sel_tdm_txdp_slot 3:2 r/w 0h txdp tdm channel slot selection to stereo channel 00b: slot 0/1 01b: slot 2/3 10b: slot 4/5 11b: slot 6/7 sel_dsp_ul_bypass 1 r/w 0h select dsp uplink bypass 0b: pass dsp 1b: bypass dsp sel_dsp_dl_bypass 0 r/w 0h select dsp downlink bypass 0b: pass dsp 1b: bypass dsp 10.26. mx -2eh: voice dsp volume control default: 2f2f h table 42. mx - 2e h: voice dsp volume control name bits read/write reset sta te description reserved 15 r 0h reserved vol_txdp_l 14 :8 r/w 2f h mono adc left channel digital volume in 0.375 db step 00h: -17.625db 2fh: 0db 7fh: 30db, 0.375db/step reserved 7 r 0h reserved vol_txdp_r 6:0 r/w 2f h mono ad c right channel digital volume in 0.375 db step 00h: -17.625db 2fh: 0db 7fh: 30db, 0.375db/step
alc5672 datasheet 79 rev. 0.75 10.27. mx -2fh: interface dac/adc data control default: 1002 h table 43. mx - 2f h: interface dac/adc data control name bits read/write reset state description sel_if1_adc2_data_in 15 r/w 0h select interface1 adc2 data input 0b: if_adc2 1b: reserved sel_if2_adc_data_in 14:12 r/w 1h select interface2 adc data input 000b: if_adc1 001b: if_adc2 010b: reserved 011b: txdc_dac 100b: txdp_adc 101b: reserved 110b: reserved 111b: reserve d sel_if2_dac_data 11:10 r/w 0h select interface2 dac data swap 00b: l/r 01b: r/l 10b: l/l 11b: r/r sel_if2_adc_data 9:8 r/w 0h select interface2 adc data swap 00b: l/r 01b: r/l 10b: l/l 11b: r/r reserved 7:0 r 2h reserved 10.28. mx -31h: speaker control 1 default: 5f00 h table 44. mx -31 h: speaker control 1 name bits read/write reset state description sel_spk_l 15 r/w 0h select speaker left channel source 0b: mono_dac_mixl 1b: stereo_dac_mixl mu_ spk _l 14 r/w 1h mute speaker left channel data 0b: unmute 1b: mute sel_spk_r 13 r/w 0h select speaker right channel source 0b: mono_dac_mixr 1b: stereo_dac_mixr mu_ spk _r 12 r/w 1h mute speaker right channel data 0b: unmute 1b: mute
alc5672 datasheet 80 rev. 0.75 name bits read/write reset state description reserved 11 :0 r f0 0h reserved 10.29. mx -3bh: recmixl control 1 default: 0000 h table 45. mx - 3b h: recmixl control 1 name bits read/write reset state description reserved 15:13 r/w 0 h reserved gain_inl_recmixl 12:10 r/w 0 h gain control for inl1 to rec left mixer 00 0 b : 0db 001 b : -3db 010 b : -6db 01 1 b : -9db 100 b : -12db 101 b : - 15db 110 b : -18db reserved 9:7 r/w 0 h reserved gain_bst2_recmixl 6:4 r/w 0 h gain control for boost 2 to rec left mixer 00 0 b : 0db 001 b : -3db 010 b : -6db 011 b : -9db 100 b : -12db 101 b : - 15db 110 b : -18db reserved 3:0 r 0h reserved 10.30. mx -3ch: recmixl control 2 default: 007 f h table 46 . mx - 3c h: recmixl control 2 name bits read/write reset state description gain_bst1_recmixl 15:13 r/w 0 h gain control for boost 1 to rec left mixer 00 0 b : 0db 001 b : -3db 010 b : -6db 011 b : -9db 100 b : -12db 101 b : - 15db 110 b : -18db reserved 12:6 r 1 h reserved mu_inl_recmixl 5 r/w 1h inl1 to recmixl mute control 0 b : un-mute 1 b : mute (- ? db ) reserved 4 r/w 1h reserved mu_bst2_recmixl 3 r/w 1h mic bst2 to recmixl mute control 0 b : un-mute 1 b : mute (- ? db ) reserved 2 r/w 1h reserved mu_bst1_recmixl 1 r/w 1h mic bst1 to recmixl mute control 0 b : un-mute 1 b : mute (- ? db ) reserved 0 r/w 1h reserved
alc5672 datasheet 81 rev. 0.75 10.31. mx -3dh: recmixr control 1 default: 0000 h table 47 . mx - 3d h: recmixr control 1 name bits read/write reset state description reserved 15:13 r/w 0 h reserved gain_inr_recmixr 12:10 r/w 0 h gain control for inr1 to rec right mixer 00 0 b : 0db 001 b : -3db 010 b : -6db 011 b : -9db 100 b : -12db 101 b : - 15db 110 b : -18db reserved 9:7 r/w 0 h reserved gain_bst2_recmixr 6:4 r/w 0 h gain control for boost 2 to rec right mixer 00 0 b : 0db 001 b : -3db 01 0 b : -6db 011 b : -9db 100 b : -12db 101 b : - 15db 110 b : -18db reserved 3:0 r 0h reserved 10.32. mx -3eh: recmixr control 2 default: 007 f h table 48 . mx - 3e h: recmixr control 2 name bits read/write reset state description gain_bst1_recmixr 15:13 r/w 0 h gain control for boost 1 to rec right mixer 00 0 b : 0db 001 b : -3db 010 b : -6db 011 b : -9db 100 b : -12db 101 b : - 15db 110 b : -18db reserved 12:6 r 1 h reserved mu_inr_recmixr 5 r/w 1h inr1 to recmixr mute control 0 b : un-mute 1 b : mute (- ? db ) reserved 4 r/w 1h reserved mu_bst2_recmixr 3 r/w 1h mic bst2 to recmixr mute control 0 b : un-mute 1 b : mute (- ? db ) reserved 2 r/w 1h reserved mu_bst1_recmixr 1 r/w 1h mic bst1 to recmixr mute control 0 b : un-mute 1 b : mute (- ? db ) reserved 0 r/w 1h reserved
alc5672 datasheet 82 rev. 0.75 10.33. mx -45h: hpomix control default: 600f h table 49 . mx - 45 h: hpomix control name bits read/write reset state description reserved 15 r 0h reserved mu_dac1_hpo 14 r/w 1h dac1 to hpo mute control 0 b : un-mute 1 b : mute (- ? db ) mu_hpvol_hpo 13 r/w 1h hpovol to hpo mute control 0 b : un-mute 1 b : mute (- ? db ) en_bst_hp 12 r/w 0h hpo gain control 0 b : 0db 1 b : -6 db reserved 11:4 r 0 h reserved mu_inr1_hpmixr 3 r/w 1h in r to hpmixr mute control 0 b : un-mute 1 b : mute (- ? db ) mu_dacr1_hpomixr 2 r/w 1h dacr1 to hpmixr mute control 0 b : un-mute 1 b : mute (- ? db ) mu_inl1_hpomixl 1 r/w 1h inl to hpmixl mute control 0 b : un-mute 1 b : mute (- ? db ) mu_dacl1_hpomixl 0 r/w 1h dacl1 to hpmixl mute control 0 b : un-mute 1 b : mute (- ? db ) 10.34. mx -4fh: outmixl control default: 0073 h table 50. mx - 4f h: outmixl control name bits read/write reset state description reserved 15:6 r 1h reserved mu_bst1_outmixl1 5 r/w 1h mute control for bst1 to outmixl1 0 b : un-mute 1 b : mute (- ? db ) mu_inl_outmixl1 4 r/w 1h mute control for inl1 to outmixl1 0 b : un-mute 1 b : mute (- ? db ) reserved 3:2 r 0h reserved mu_dacl2_outmixl1 1 r/w 1h mute control for dacl2 to outmixl1 0 b : un-mute 1 b : mute (- ? db )
alc5672 datasheet 83 rev. 0.75 name bits read/write reset state description mu_dacl1_outmixl1 0 r/w 1h mute control for dacl1 to outmixl1 0 b : un-mute 1 b : mute (- ? db ) 10.35. mx -52h: outmixr control default: 00d3 h table 51. mx - 52 h: outmixr control 3 name bits read/write reset state description reserved 15:7 r 1h reserved mu_bst2_outmixr1 6 r/w 1h mute control for bst2 to outmixr1 0 b : un-mute 1 b : mute (- ? db ) reserved 5 r 0h reserved mu_inr_outmixr1 4 r/w 1h mute control for inr1 to outmixr1 0 b : un-mute 1 b : mute (- ? db ) reserved 3:2 r 0h reserved mu_dacr2_outmixr1 1 r/w 1h mute control for dacr2 to outmixr1 0 b : un-mute 1 b : mute (- ? db ) mu_dacr1_outmixr1 0 r/w 1h mute control for dacr1 to outmixr1 0 b : un-mute 1 b : mute (- ? db ) 10.36. mx -53h: loutmix control default: f 000 h table 52. mx - 53 h: loutmix control name bits read/write reset state description mu_dacl1_lout1 15 r/w 1h mute dacl1 to lout1 mixer 0 b : un-mute 1 b : mute (- ? db ) mu_dacr1_lout1 14 r/w 1h mute dacr1 to lout1 mixer 0 b : un-mute 1 b : mute (- ? db ) mu_outmixl1_lout1 13 r/w 1h mute output left volume 1 to lout1 mixer 0 b : un-mute 1 b : mute (- ? db ) mu_outmixr1_lout1 12 r/w 1h mute output right volume 1 to lout1 mixer 0 b : un-mute 1 b : mute (- ? db )
alc5672 datasheet 84 rev. 0.75 name bits read/write reset state description bst_lout1 11 r/w 0 h gain control for all path to lout1 mixer 0 b : 0db 1 b : - 6db reserved 10:0 r 0h reserved 10.37. mx -61h: power management control 1 default: 0000 h table 53. mx - 61 h: power management control 1 name bits read/write reset state description en_i2s1 15 r/w 0h i2s1 digital interface power control 0b: power down 1b: power on en_i2s2 14 r/w 0h i2s2 digital interface power control 0b: power down 1b: power on reserved 13 r/w 0h reserved pow_dac_l_1 12 r/w 0h analog dacl1 power control 0b: power down 1b: power on pow_dac_r_1 11 r/w 0h analog dacr1 power control 0b: power down 1b: power on reserved 10:8 r 0h reserved pow_dac_l_2 7 r/w 0h analog dacl2 power control 0b: power down 1b: power on pow_dac_r_2 6 r/w 0h analog dacr2 power control 0b: power down 1b: power on reserved 5:3 r 0h reserved pow_adc_l 2 r/w 0h analog adcl power control 0b: power down 1b: power on pow_adc_r 1 r/w 0h analog adcr power control 0b: power down 1b: power on reserved 0 r 0h reserved
alc5672 datasheet 85 rev. 0.75 10.38. mx -62h: power management control 2 default: 0000 h table 54. mx - 62 h: power management control 2 name bits read/write reset state description pow_adc_stereo_filte r 15 r/w 0h stereo1 adc digital filter power control 0b: power down 1b: power on pow_adc_monol_filte r 14 r/w 0h mono adc_l digital filter power control 0b: power down 1b: power on pow_adc_monor_filte r 13 r/w 0h mono adc_r digital filter power control 0b: power down 1b: power on pow_i2s_dsp 12 r/w 0h i2s interface for dsp power control 0b: power down 1b: power on pow_dac_stereo1_filt er 11 r/w 0 h power on dac stereo1 filter 0b: power down 1b: power on pow_dac_monol_filte r 10 r/w 0 h power on dac mono left filter 0b: power down 1b: power on pow_dac_monor_filte r 9 r/w 0 h power on dac mono right filter 0b: power down 1b: power on pow_adc_stereo2_filt er 8 r/w 0 h power on adc stereo2 filter 0b: power down 1b: power on pow_spk 7 r/w 0h power on speaker 0b: power down 1b: power on reserved 6:0 r 0h reserved 10.39. mx -63h: power management control 3 default: 00c 0 h table 55. mx - 63 h: power management control 3 name bits read/write reset state description pow_vref1 15 r/w 0h vref1 power control 0b: power down 1b: power on en_fastb1 14 r/w 0h vref1 fast mode control 0b: fast vref 1b: slow vref, (for good an alog performance)
alc5672 datasheet 86 rev. 0.75 name bits read/write reset state description pow_main_bias 13 r/w 0h mbias power control 0b: power down 1b: power on pow_lout 12 r/w 0h loutmix power control 0b: power down 1b: power on pow_bg_bias 11 r/w 0h mbias bandgap power control 0b: power down 1b: power on reserv ed 10:8 r 0h reserved en_l_hp 7 r/w 1h left headphone amp power control 0b: power down 1b: power on en_r_hp 6 r/w 1h right headphone amp power control 0b: power down 1b: power on en_amp_hp 5 r/w 0h improve hp amp driving 0b: disable 1b: enable pow_vref2 4 r/w 0h vref2 power control 0b: power down 1b: power on en_fastb2 3 r/w 0h vref2 fast mode control 0b: fast vref 1b: slow vref, (for good analog performance) dvo_ldo 2:0 r/w 3 h selection of the ldo output 000b: reserved 001b: reserv ed 010b: 1.0v 011b: 1.2v 100b: 1.25v 101b: 1.3v 110b: 1.35v 111b: 1.4v 10.40. mx -64h: power management control 4 default: 0000 h table 56. mx - 64 h: power management control 4 name bits read/write reset state description pow_bst1 _1 15 r/w 0h mic bst1 power control 1 0b: power down 1b: power on reserved 14 r/w 0h reserved pow_bst2 _1 13 r/w 0h mic bst2 power control 1 0b: power down 1b: power on
alc5672 datasheet 87 rev. 0.75 name bits read/write reset state description reserved 12 r/w 0h reserved pow_micbias1 _1 11 r/w 0h micbias1 power control 1 0b: power down 1b: p ower on reserved 10 r/w 0h reserved pow_pll 9 r/w 0h pll power control 0b: power down 1b: power on reserved 8: 7 r 0h reserved pow_bst1_2 6 r/w 0h mic bst1 power control 2 0b: power down 1b: power on reserved 5 r 0h reserved pow_bst2_2 4 r/w 0h mic bst2 power control 2 0b: power down 1b: power on reserved 3 r 0h reserved pow_jd1 2 r/w 0h jd1 power control 0b: power down 1b: power on pow_jd2 1 r/w 0h jd2 power control 0b: power down 1b: power on reserved 0 r 0h reserved 10.41. mx -65h : power management control 5 default: 0000 h table 57. mx - 65 h: power management control 5 name bits read/write reset state description pow_outmixl 15 r/w 0h outmixl & vol power control 0b: power down 1b: power on pow_outmixr 14 r/w 0h outmixr & vol power control 0b: power down 1b: power on reserved 13 :12 r 0h reserved pow_recmixl 11 r/w 0h recmixl power control 0b: power down 1b: power on pow_recmixr 10 r/w 0h recmixr power control 0b: power down 1b: power on reserved 9:0 r 0h reserved
alc5672 datasheet 88 rev. 0.75 10.42. mx -66h: power management control 6 default: 0000 h table 58. mx - 66 h: power management control 6 name bits read/write reset state description reserved 15 :12 r 0h reserved pow_hpovoll 11 r/w 0h hp mixl & vol power control 0b: power down 1b: power o n pow_hpovolr 10 r/w 0h hp mixr & vol power control 0b: power down 1b: power on pow_inlvol 9 r/w 0h inlvol power control 0b: power down 1b: power on pow_inrvol 8 r/w 0h inrvol power control 0b: power down 1b: power on reserved 7: 6 r 0h reserved pow_mic_in_det 5 r/w 0h mic_in_det power control 0b: power down 1b: power on reserved 4:1 r 0h reserved pow_micbias1_2 0 r/w 0h micbias1 power control 2 0b: power down 1b: power on 10.43. mx -6ah: private register index default: 0000 h table 59. mx - 6a h: private register index name bits read/write reset state description reserved 15:8 r 0h reserved pr_index 7:0 r/w 0h pr register index 10.44. mx -6ch: private register data default: 0000 h table 60. mx - 6c h: private register data name bits read/write reset state description pr_data 15:0 r/w 0h pr register data
alc5672 datasheet 89 rev. 0.75 10.45. mx -70h: i2s1 digital interface control default: 8000 h table61. mx - 70 h: i2s1 digital interface control name bits read/write reset state description sel_i2s1_ms 15 r/w 1 h i2s1 digital interface mode control 0b: master mode 1b: slave mode reserved 14:12 r 0h reserved en_i2s1_out_comp 11:10 r/w 0h i2s1 output data compress (for adcdat1 output) 00 b : off 01 b : law 10 b : a law 11 b : reserved en_i2s1_in_comp 9:8 r/w 0h i2s1 input data compress (for dacdat1 input) 00 b : off 01 b : law 10 b : a law 11 b : reserved inv_i2s1_bclk 7 r /w 0h i2s1 bclk polarity control 0 b : normal 1 b : invert reserved 6:4 r 0h reserved sel_i2s1_len 3:2 r /w 0 h i2s1 data length selection 00 b : 16 bits 01 b : 20 bits 10 b : 24 bits 11 b : 8 bits sel_i2s1_format 1:0 r /w 0 h i2s1 pcm data format selection 00 b : i 2 s format 01 b : left justified 10 b : pcm mode a (lrck one plus at master mode) 11 b : pcm mode b (lrck one plus at master mode) 10.46. mx -71h: i2s2 digital interface control default: 8000 h table 62. mx - 71 h: i2s2 digital interface control name bits read/write reset state description sel_i2s2_ms 15 r/w 1 h i2s2 digital interface mode control 0b: master mode 1b: slave mode reserved 14:12 r 0h re served
alc5672 datasheet 90 rev. 0.75 name bits read/write reset state description en_i2s2_out_comp 11:10 r/w 0h i2s2 output data compress (for adcdat2 output) 00 b : off 01 b : law 10 b : a law 11b: reserved en_i2s2_in_comp 9:8 r/w 0h i2s2 input data compress (for dacdat2 input) 00 b : off 01 b : law 10 b : a law 11b: res erved inv_i2s2_bclk 7 r /w 0h i2s2 bclk polarity control 0b: normal 1b: invert reserved 6 :4 r 0h reserved sel_i2s2_len 3:2 r /w 0 h i2s2 data length selection 00b: 16 bits 01b: 20 bits 10b: 24 bits 11b: 8bits sel_i2s2_format 1:0 r /w 0 h i2s2 pcm data format selection 00b: i 2 s format 01b: left justified 10b: pcm mode a (lrck one plus at master mode) 11b: pcm mode b (lrck one plus at master mode) 10.47. mx -73h: adc/dac clock control default: 1114 h table 63. mx -73 h: adc/dac clock control name bits read/write reset state description reserved 15 r 0h reserved sel_i2s_pre_div1 14:12 r /w 1 h i2s clock pre-divider 1 000b: 1 001b: 2 010b: 3 011b: 4 100b: 6 101b: 8 110b: 12 111b: 16 sel_i2s_bclk_ms2 11 r /w 0h i2s2 master mode clock relative of bclk and lrck 0b: 16bits (32fs) 1b: 32bits (64fs)
alc5672 datasheet 91 rev. 0.75 name bits read/write reset state description sel_i2s_pre_div2 10:8 r /w 1 h i2s pre-divider 2 000b: 1 001b: 2 010b: 3 011b: 4 100b: 6 101b: 8 110b: 12 111b: 16 reserved 7:4 r /w 1h reserved sel_dac_osr 3:2 r/w 1 h stereo dac over sample rate select 00b: 128fs 01b: 64fs 10b: 32fs 11 b: reserved sel_adc_osr 1:0 r/w 0h stereo adc over sample rate select 00b: 128fs 01b: 64fs 10b: 32fs 11 b: reserved 10.48. mx -74h: adc/dac hpf control default: 0e 00 h table 64. mx -74 h: adc/dac hpf control name bits read/write reset state description reserved 15:12 r 0h reserved dehpf_en 11 r/w 1 h enable stereo/mono dac high pass filter 0 b: disable 1b: enable adhpf_en 10 r/w 1h enable stereo1/2 adc high pass filter 0b: disable 1b: enable mono_adhpf_en 9 r/w 1h enable mono adc high pass filter 0b: disable 1b: enable reserved 8 :0 r 0h reserved
alc5672 datasheet 92 rev. 0.75 10.49. mx -75h: digital microphone control 1 default: 1505 h table 65. mx - 75 h: digital microphone control 1 name bits read/write reset state description en_dmic1 15 r /w 0 h enable dmic1 interface 0b: disable 1b: enable (output dmic clock) en_dmic2 14 r /w 0 h enable dmic2 interface 0b: disable 1b: enable (output dmic clock) sel_dmic_l_edge_ster eo1 13 r/w 0h stereo1 adc filter dmic left channel source control (synchronous mode) 0b: latch from falling edge 1b: latch from rising edge sel_dmic_r_edge_ster eo1 12 r/w 1h stereo1 adc filter dmic right channel source control (synchronous mode) 0b: latch from fall ing edge 1b: latch from rising edge reserved 11 r/w 0 h reserved dmic2_data_pin_shar e 10 r/w 1h select the pin share of dmic2_data 0b:gpio8 1b:in3n sel_dmic_l_edge_ster eo2 9 r/w 0h stereo2 adc filter dmic left channel source control (synchronous mode) 0b: latch from falling edge 1b: latch from rising edge sel_dmic_r_edge_ster eo2 8 r/w 1h stereo2 adc filter dmic right channel source control (synchronous mode) 0b: latch from falling edge 1b: latch from rising edge sel_dmic_clk 7:5 r/w 0h dmic clock rate control 000b: 256*fs/2 001b: 256*fs/3 010b: 256*fs/4 011b: 256*fs/6 100b: 256*fs/8 101b: 256*fs/12 en_dmic3 4 r /w 0 h enable dmic3 interface 0b: disable 1b: enable (output dmic clock) sel_dmic_l_edge_mo no 3 r/w 0h mono adc filter dmic left channel source control (synchronous mode) 0b: latch from falling edge 1b: latch from rising edge sel_dmic_r_edge_mo no 2 r/w 1h mono adc filter dmic right channel source control (synchronous mode) 0b: latch from falling edge 1b: latch from risi ng edge
alc5672 datasheet 93 rev. 0.75 name bits read/write reset state description dmic1_data_pin_shar e 1:0 r/w 1h select the pin share of dmic1_data 00b: gpio6 01b: in2p 10b: reserved 11b: reserved 10.50. mx -76h: digital microphone control 2 default: 001 5 h table 66 . mx -76 h: digital microphone control 2 name bits read/write reset state description reserved 15:8 r 0h reserved dmic3_data_pin_shar e 7:6 r/w 0h select the pin share of dmic3_data 00b: reserved 01b: reserved 10b: gpio5 (dacdat2) 11b: reserved sel_dmic3_lpf_l_edge 5 r/w 0h dmic3 data left channel source control (asynchronous mode) 0b: latch from falling edge 1b: latch from rising edge sel_dmic3_lpf_r_edg e 4 r/w 1h dmic3 data right channel source control (asynchronous mode) 0b: latch from falling edge 1b: latch from rising edge sel_dmic2_lpf_l_edge 3 r/ w 0h dmic2 data left channel source control (asynchronous mode) 0b: latch from falling edge 1b: latch from rising edge sel_dmic2_lpf_r_edg e 2 r/w 1h dmic2 data right channel source control (asynchronous mode) 0b: latch from falling edge 1b: latch fr om rising edge sel_dmic1_lpf_l_edge 1 r/w 0h dmic1 data left channel source control (asynchronous mode) 0b: latch from falling edge 1b: latch from rising edge sel_dmic1_lpf_r_edg e 0 r/w 1h dmic1 data right channel source control (asynchronous mode) 0 b: latch from falling edge 1b: latch from rising edge
alc5672 datasheet 94 rev. 0.75 10.51. mx -77h: tdm interface control 1 default: 0c00 h table 67 . mx - 77 h: tdm interface control 1 name bits read/write reset state description reserved 15 r/w 0h reserved mode_sel 14 r/w 0h i2s / tdm mode control 0b: normal i2s mode 1b: tdm mode tdmslot_sel 13:12 r/w 0h tdm channel number select 00b: 2ch 01b: 4ch 10b: 6ch 11b: 8ch channel_length 11:10 r/w 3h tdm channel length 00b: 16bit (for slave mode and master mode) 01b: 20bit (f or slave mode) 10b: 24bit (for slave mode) 11b: 32bit (for slave mode and master mode) rx_adc_data_sel 9 r/w 0h adc data to adcdat data location 0b: 1l/1r/2l/2r/3l/3r/4l/4r 1b: 2l/2r/1l/1r/4l/4r/3l/3r reserved 8 r 0h reserved sel_i2s_rx_ch2 7:6 r/ w 0h data swap for slot0/1 in adcdat1 00 b : l/r 01 b : r/l 10 b : l/l 11 b : r/r sel_i2s_rx_ch4 5:4 r/w 0h data swap for slot2/3 in adcdat1 00 b : l/r 01 b : r/l 10 b : l/l 11 b : r/r sel_i2s_rx_ch6 3:2 r/w 0h data swap for slot4/5 in adcdat1 00 b : l/r 01 b : r/l 10 b : l/l 11 b : r/r sel_i2s_rx_ch8 1:0 r/w 0h data swap for slot6/7 in adcdat1 00 b : l/r 01 b : r/l 10 b : l/l 11 b : r/r
alc5672 datasheet 95 rev. 0.75 10.52. mx -78h: tdm interface control 2 default: 4000 h table 68 . mx -78 h: tdm interface control 2 name bits read/write reset state description sel_i2s_lrck_polarity 15 r/w 0h tdm interface lrck polarity inverter 0b: normal 1b: invert reserved 14:12 r/w 4h reserved lrck_pulse_sel 11 r/w 0h lrck pulse width select (master mode only) 0b: one bclk width 1b: one channel slot width reserved 10:8 r/w 0h reserved mute_tdm2_outl 7 r/w 0h if1_adc1 left data mute/un-mute control 0b : un-mute 1b : mute mute_tdm2_outr 6 r/w 0h if1_adc1 right data mute/un-mute control 0b : un-mute 1b : mute mute_tdm4_outl 5 r/w 0h if1_adc2 left data mute/un-mute control 0b : un-mute 1b : mute mute_tdm4_outr 4 r/w 0h if1_adc2 right data mute/un-mute control 0b : un-mute 1b : mute mute_tdm6_outl 3 r/w 0h if1_adc3 left data mute/un-mute control 0b : un-mute 1b : mute mute_tdm6_outr 2 r/w 0h if1_adc3 right data mute/un-mute control 0b : un-mute 1b : mute mute_tdm8_outl 1 r/w 0h if1_adc4 left data mute/un-mute control 0b : un-mute 1b : mute mute_tdm8_outr 0 r/w 0h if1_adc4 right data mute/un- mut e control 0b : un-mute 1b : mute
alc5672 datasheet 96 rev. 0.75 10.53. mx -79h: tdm interface control 3 default: 0123 h table 69 . mx -79 h: tdm interface control 3 name bits read/write reset state description reserved 15 r 0h reserved sel_i2s_tx_l_ch2 14:12 r/w 0h if1_dac1_l data selection 000b: slot0 001b: slot1 010b: slot2 011b: slot3 100b: slot4 101b: slot5 110b: slot6 111b: slot7 reserved 11 r 0h reserved sel_i2s_tx_r_ch2 10:8 r/w 1h if1_dac1_r data selection 000b: slot0 001b: slot1 010b: s lot2 011b: slot3 100b: slot4 101b: slot5 110b: slot6 111b: slot7 reserved 7 r 0h reserved sel_i2s_tx_l_ch4 6:4 r/w 2h if1_dac2_l data selection 000b: slot0 001b: slot1 010b: slot2 011b: slot3 100b: slot4 101b: slot5 110 b: slot6 111b: slot7 reserved 3 r 0h reserved sel_i2s_tx_r_ch4 2:0 r/w 3h if1_dac2_r data selection 000b: slot0 001b: slot1 010b: slot2 011b: slot3 100b: slot4 101b: slot5 110b: slot6 111b: slot7
alc5672 datasheet 97 rev. 0.75 10.54. mx -7fh: clock control 1 default: 11 00 h table 70. mx -7f h: clock control 1 name bits read/write reset state description reserved 15 :4 r 11 0h reserved sel_dsp_asrc0 3:0 r /w 0 h select the clock source for dsp 0000b: clk_sys 0001b: clk_i2s1_ asrc 0010b: clk_i2s2_ asrc 0011b: re served 0100b: reserved 0101b: clk_sys2 others: reserved 10.55. mx -80h: global clock control default: 0000 h table 71. mx - 80 h: global clock control name bits read/write reset state description sel_sysclk1 15:14 r/w 0h system clock source mux control 00b: mclk 01b: pll 10 b: internal clock 11b: reserved sel_pll_sour 13:11 r/w 0h pll source selection 0 00b: from mclk 0 01b: from bclk1 0 10b: from bclk2 others: reserved reserved 10 :4 r 0h reserved sel_pll_pre_div 3 r/w 0h pll pre-divider 0b: 1 1b : 2 reserved 2:0 r 0h reserved
alc5672 datasheet 98 rev. 0.75 10.56. mx -81h: pll control 1 default: 0000 h table 72. mx - 81 h: pll control 1 name bits read/write reset state description pll_n_code 15:7 r /w 0 h pll n[8:0] code 000000000 b : div 2 000000001 b : div 3 111111111 b : div 513 reserved 6:5 r 0h reserved pll_k_code 4:0 r /w 0 h pll k[4:0] code 00000b: div 2 00001b: div 3 11111b: div 33 10.57. mx -82h: pll control 2 default: 0000 h table 73. mx - 82 h: pll control 2 name bits read/write reset state description pll_m_code 15:12 r /w 0 h pll m[3:0] code 0000 b : div 2 0001 b : div 3 1111 b : div 17 pll_m_bypass 11 r/w 0h bypass pll m code 0b : no bypass 1b : bypass reserved 10:0 r 0h reserved
alc5672 datasheet 99 rev. 0.75 10.58. mx -83h: asrc control 1 default: 0000 h table 74. mx - 83 h: asrc control 1 name bits read/write reset state description reserved 15:13 r 0h reserved en_i2s2_asrc 12 r/w 0h enable i2s2 asrc function 0b: disable 1b: enable en_i2s1_asrc 11 r/w 0h enable i2s1 asrc function 0b: disable 1b: enable sel_stereo_dac_mode 10 r/w 0 h enable dac asrc for stereo dac 0b : disable 1b : enable sel_mono_dac_l_mo de 9 r/w 0h enable dac asrc for mono left path 0b : disable 1b : enable sel_mono_dac_r_mo de 8 r/w 0h enable dac asrc for mono right path 0b : disable 1b : enable en_dmic_asrc_stereo 1 7 r /w 0 h enable dmic asrc for stereo1 path 0b : disable 1b : enable en_dmic_asrc_stereo 2 6 r /w 0 h enable dmic asrc for stereo2 path 0b : disable 1b : enable en_dmic_asrc_monol 5 r /w 0 h enable dmic asrc for mono left path 0b : disabl e 1b : enable en_dmic_asrc_monor 4 r /w 0 h enable dmic asrc for mono right path 0b : disable 1b : enable en_adc_asrc_stereo1 3 r /w 0 h enable adc asrc for stereo1 path 0b : disable 1b : enable en_adc_asrc_stereo2 2 r /w 0 h enable adc asrc for stereo2 path 0b : disable 1b : enable en_adc_asrc_monol 1 r /w 0 h enable adc asrc for mono left path 0b : disable 1b : enable en_adc_asrc_monor 0 r /w 0 h enable adc asrc for mono right path 0b : disable 1b : enable
alc5672 datasheet 100 rev. 0.75 10.59. mx -84h: asrc control 2 default: 000 0 h table 75 . mx - 84 h: asrc control 2 name bits read/write reset state description sel_da_filter_stereo_a src 15:12 r /w 0 h select the asrc clock source for da stereo filter 0000b : clk_sys 0001b : clk_i2s1_asrc 0010b : clk_i2s2_asrc 0011b : reserved 0100b : reserved 0101b : clk_sys2 others: reserved sel_da_filter_monol_ asrc 11:8 r /w 0 h select the asrc clock source for da mono left filter 0000b: clk_sysy_div_out 0001b: clk_i2s1_asrc 0010b: clk_i2s2_asrc 0011b: reserved 0100b: reserved 0101b: clk_sys2 others: reserved sel_da_filter_monor_ asrc 7:4 r /w 0 h select the asrc clock source for da mono right filter 0000b: clk_sysy_div_out 0001b: clk_i2s1_asrc 0010b: clk_i2s2_asrc 0011b: reserved 0100b: reserved 0101b: clk_sys2 others: reserved sel_ad_filter_stereo1_ asrc 3:0 r /w 0 h select the asrc clock source for ad stereo1 filter 0000b: clk_sysy_div_out 0001b: clk_i2s1_asrc 0010b: clk_i2s2_asrc 0011b: reserved 0100b: reserved 0101b: clk_sys2 others: reserved
alc5672 datasheet 101 rev. 0.75 10.60. mx -85h: asrc control 3 default: 0000 h table 76 . mx - 85 h: asrc control 3 name bits read/write reset state description sel_up_filter_asrc 15:12 r/w 0h select the asrc clock source for up sample rate filter 0000b: clk_sysy_div_out 0001b: clk_i2s1_ asrc 0010b: clk_i2s2_asrc 0011b: reserved 0100b: reserved 0101b: clk_sys2 others: reserved sel_down_filter_asrc 11:8 r/w 0h select the asrc clock source for down sample rate filter 0000b: clk_sysy_div_out 0001b: clk_i2s1_asrc 0010b: clk_i2s2_asrc 0011b: reserved 0100b : reserved 0101b: clk_sys2 others: reserved sel_ad_filter_monol_ asrc 7:4 r/w 0h select the asrc clock source for ad mono left filter 0000b: clk_sysy_div_out 0001b: clk_i2s1_asrc 0010b: clk_i2s2_asrc 0011b: reserved 0100b: reserved 0101b: clk_sys 2 others: reserved sel_ad_filter_monor_ asrc 3:0 r/w 0h select the asrc clock source for ad mono right filter 0000b: clk_sysy_div_out 0001b: clk_i2s1_asrc 0010b: clk_i2s2_asrc 0011b: reserved 0100b: reserved 0101b: clk_sys2 others: reserved
alc5672 datasheet 102 rev. 0.75 10.61. mx -8ah: asrc control 4 default: 0000 h table 77 . mx -8a h: asrc control 4 name bits read/write reset state description i2s1_asrc_prediv 15:14 r /w 0 h set the i2s1 clock division for asrc mode 00b: div1 01b: div2 10b: div3 11b: reserved sel_i2s1_asrc 13:12 r /w 0 h select the asrc source of asrc 0 0b : asrc1 0 1b : asrc2 10b : reserved 11b: reserved i2s2_asrc_prediv 11:10 r /w 0 h set the i2s2 clock division for asrc mode 00 b : div1 0 1b : div2 10b : div3 11b: reserved sel_i2s2_asrc 9:8 r /w 0 h select the asrc source of i2s2 00 b : asrc1 0 1b : asrc2 10b : reserved 11b: reserved reserved 7:0 r/w 0h reserved 10.62. mx -8ch: asrc control 5 default: 0007 h table 78 . mx -8c h: asrc control 5 name bits read/write reset state description sel_ad_filter_stereo2_asrc 15:12 r /w 0 h select the asrc clock source for ad stereo2 filter 0000b: clk_sysy_div_out 0001b: clk_i2s1_asrc 0010b: clk_i2s2_asrc 0011b: reserved 0100b: reserved 0101b: clk_sys2 others: reserved reserved 11 :0 r /w 7 h reserved
alc5672 datasheet 103 rev. 0.75 10.63. mx -8eh: hp amp control 1 default: 0004 h table 79 . mx - 8e h: hp amp control 1 name bits read/write reset state description smttrig_hp 15 r/w 0h enable softgen trigger for soft mute depop 0b: disable 1b: enable reserved 14:10 r/w 0h reserved en_smt_l_hp 9 r/w 0h enable hp_l mute/un-mute depop 0b: disbale 1b: enable en_smt_r_hp 8 r/w 0h enable hp_r mute/un-mute depop 0b: disbale 1b: enable pdn_hp 7 r/w 0h capless depop power down control 0 b: disbale 1b: enable softgen_rstn 6 r/w 0h reset softgen to initialize softp=1 0b: disbale 1b: reset softgen_rstp 5 r/w 0h reset softgen to initialize softp=0 0b: disbale 1b: reset en_out_hp 4 r/w 0h enable headphone output 0b: disable 1b: en able pow_pump_hp 3 r/w 0h charge pump power control 0b: power down 1b: power on en_softgen_hp 2 r/w 1h power on soft generator 0b: power down 1b: power on reserved 1 r/w 0h reserved pow_capless 0 r/w 0h hp amp all power on control 0b: power do wn 1b: power on 10.64. mx -8fh: hp amp control 2 default: 1100 h table 80. mx - 8f h: hp amp control 2 name bits read/write reset state description reserved 15:14 r 0h reserved depop_mode_hp 13 r/w 0h select hp depop mode 0b: depop mode 1 1b: depop mode 2 reserved 12:7 r/w 22h reserved
alc5672 datasheet 104 rev. 0.75 name bits read/write reset state description en_depop_mode1 6 r/w 0h hp depop mode 1 control 0b: disbale 1b: enable reserved 5:0 r/w 0h reserved 10.65. mx -93h: micbias control default: 0 000 h table 81. mx - 93 h: micbias control name bits read/write reset state description sel_micbias1 15 r /w 0 h micbias1 output voltage control 0 b: 0.9 * micvdd 1b: 0.75 * mic vdd reserved 14 :12 r /w 0 h reserved pow_mic1_ovcd 11 r /w 0 h micbias1 short current detector control 0 b : disable 1 b : enable mic1_ovcd_th_sel 10:9 r /w 0 h micbias1 short current detector threshold 00 b : 640ua 01 b : 1 28 0ua 1x b : 192 0ua note: tolerance is 200ua reserved 8:6 r /w 0 h reserved ckn_micbias 5 r/w 0h micbias clock power 0b: disable 1b: enable pow_clk_int 4 r/w 0h internal clock power 0b: disable 1b: enable sel_irq_debounce 3 r/w 0h select irq de-bounce clock 0b: mclk 1b: internal clock reserved 2:0 r 0 h reserved 10.66. mx -94h: jd1 control default: 0000 h table 82. mx -94 h: jd1 control name bits read/write reset state description reserved 15:2 r /w 0 h reserved sel_mode_jd1 1:0 r /w 0 h jd1 mode control 00b: mode -0, two port jack detection 01b: mode -1, one port jack detection others: reserved
alc5672 datasheet 105 rev. 0.75 10.67. mx - ae h: adc path eq control 1 default: 6 000 h table 83. mx - ae h: adc path eq control 1 name bits read/write reset state description reserved 15 r 0h reserved ad_eq_param_update 14 r/w 1h adc path eq parameter update control 0 b : busy (waiting for cross) 1 b : stand- by write 1 to update parameter reserved 13:6 r/w 80h reserved ad_eq_hpf1_status 5 r 0h adc path eq high pass filter (hpf1) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it. ad_eq_bpf4_status 4 r 0h adc path eq band-4 (bp4) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it. ad_eq_bpf3_status 3 r 0h adc path eq band-3 (bp3) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it. ad_eq_bpf2_status 2 r 0h adc path eq band-2 (bp2) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it. ad_eq_bpf1_status 1 r 0h adc path eq band-1 (bp1) status. 0b: normal 1b: overflow . this bit is set if overflow had ever occurred. write 1 to clear it. ad_eq_lpf_status 0 r 0h adc path eq low pass filter (lpf) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it.
alc5672 datasheet 106 rev. 0.75 10.68. mx -afh: adc path eq control 2 default: 0000 h table 84. mx -af h: adc path eq control 2 name bits read/write reset state description reserved 15:9 r 0h reserved ad_eq_lpf_tpy 8 r/w 0h adc path 1 st eq low pass filter mode control (lpf) 0 b : low frequency shelving filter 1 b : 1 st order butterworth lpf (-20db per decade) ad_eq_hpf1_tpy 7 r/w 0h adc path 1 st eq high pass filter1 mode control (hpf1) 0 b : high frequency shelving filter 1 b : 1 st order butterworth hpf (-20db per decade) reserved 6 r 0h reserved ad_eq_hpf1_en 5 r/w 0h adc path eq 1 st high pass filter (hpf1) control. 0 b : disabled (bypass) and reset 1 b : enabled ad_eq_bpf4_en 4 r/w 0h adc path 2 nd eq band-4 (bp4) shelving filter control. 0 b : disabled and reset 1 b : enabled. ad_eq_bpf3_en 3 r/w 0h adc path 2 nd eq band-3 (bp3) shelving filter control. 0 b : disabled and reset 1 b : enabled. ad_eq_bpf2_en 2 r/w 0h adc path 2 nd eq band-2 (bp2) shelving filter control. 0 b : disabled and reset 1 b : enabled. ad_eq_bpf1_en 1 r/w 0h adc path 2 nd eq band-1 (bp1) shelving filter control. 0 b : disabled and reset 1 b : enabled. ad_eq_lpf_en 0 r/w 0h adc path 1 st eq low pass filter (lpf) filter control. 0 b : disabled and reset 1 b : enabled.
alc5672 datasheet 107 rev. 0.75 10.69. mx - b0 h: dac path eq control 1 default: 6 000 h table 85. mx - b0 h: dac path eq control 1 name bits read/write reset state description reserved 15 r 0h reserved da_eq_param_update 14 r/w 1h dac path eq parameter update control 0 b : busy (waiting for cross) 1 b : stand- by write 1 to update parameter reserved 13:8 r/w 20h reserved da_eq_lpf1_status 7 r 0h dac path eq low pass filter (lpf2) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it. da_eq_hpf2_status 6 r 0h dac path eq high pass filter (hpf2) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it. da_eq_hpf1_status 5 r 0h dac path eq high pass filter (hpf1) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it. da_eq_bpf4_status 4 r 0h dac path eq band-4 (bp4) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it. da_eq_bpf3_status 3 r 0h dac path eq band-3 (bp3) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it. da_eq_bpf2_status 2 r 0h dac path eq band-2 (bp2) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it. eq_biquad_wclr 1 r 0h dac path eq band-1 (biquad type) status. 0b: normal 1b: overflow. this bit is set if overflow had ever occurred. write 1 to clear it. reserved 0 r 0h reserved
alc5672 datasheet 108 rev. 0.75 10.70. mx - b1 h: eq control 2 default: 0000 h table 86. mx - b1 h: eq control 2 name bits read/write reset state description reserved 15:14 r 0h reserved da_eq_lpf1_tpy_r 13 r/w 0h dac path right channel 1 st eq low pass filter mode control (lpf2) 0 b : low frequency shelving filter 1 b : 1 st order butterworth lpf (-20db per decade) da_eq_lpf1_tpy_l 12 r/w 0h dac path left channel 1 st eq low pass filter mode control (lpf2) 0 b : low frequency shelving filt er 1 b : 1 st order butterworth lpf (-20db per decade) reserved 11:10 r 0h reserved da_eq_hpf1_tpy_r 9 r/w 0h dac path right channel 1 st eq high pass filter1 mode control 0 b : high frequency shelving filter 1 b : 1 st order butterworth hpf (-20db per decad e) da_eq_hpf1_tpy_l 8 r/w 0h dac path left channel 1 st eq high pass filter1 mode control 0 b : high frequency shelving filter 1 b : 1 st order butterworth hpf (-20db per decade) da_eq_lpf1_en 7 r/w 0h dac path 1 st eq low pass filter (lpf2) filter control. 0 b : disabled and reset 1 b : enabled. da_eq_hpf2_en 6 r/w 0h dac path eq 2 nd high pass butterworth filter (hpf) control. 0 b : disabled (bypass) and reset 1 b : enabled da_eq_hpf1_en 5 r/w 0h dac path eq 1 st high pass filter (hpf1) control. 0 b : disabled (bypass) and reset 1 b : enabled da_eq_bpf4_en 4 r/w 0h dac path 2 nd eq band-4 (bp4) shelving filter control. 0 b : disabled and reset 1 b : enabled. da_eq_bpf3_en 3 r/w 0h dac path 2 nd eq band-3 (bp3) shelving filter control. 0 b : disabled and reset 1 b : enabled. da_eq_bpf2_en 2 r/w 0h dac path 2 nd eq band-2 (bp2) shelving filter control. 0 b : disabled and reset 1 b : enabled. eq_biquad_en 1 r/w 0h dac path 2 nd eq band-1 (biquad type) shelving filter control. 0 b : disabled and reset 1 b : enabled. reserved 0 r 0h reserved
alc5672 datasheet 109 rev. 0.75 10.71. mx -b2h: drc control 1 default: 0000 h table 87. mx -b2 h: drc control 1 name bits read/write reset state description reserved 15:7 r 0h reserved alc_thmin_fast_rc_e n 6 r/w 0h drc thmin mode fast recover control 0b: disable fast recover 1b: enable fast recover alc_thmin 5:0 r/w 0h drc thmin mode threshold level control 00h: - 60db 01h: -60.75db 02h: -61.5db 2eh: -94.5db, 0.75db/step 10.72. mx-b3h: drc control 2 default: 001f h table 88. mx -b3 h: drc control 2 name bits read/write reset state description reserved 15 r 0h reserved alc_noise_gate_ht 14:12 r/w 0h alc noise gate hold time control 000b: 0 sample 001b: 128 samples 010b: 256 s amples 111b: 896 samples alc_ft_boost 11:6 r/w 0h alc digital pre-boost (0.75db/step) 00h= 0db 01h= 0.75db 02h= 1.5db 03h= 2.25db 27h= 29.25dbfs others: reserved alc_bk_gain_r 5:0 r/w 1fh alc right channel digital post-boost (0.375db/step) 00 h= -11.625db 3fh= 12db
alc5672 datasheet 110 rev. 0.75 10.73. mx -b4h: dr c control 3 default: 2206 h table 89. mx -b4 h: dr c control 3 name bits read/write reset state description sel _dr c_agc 15:14 r/w 0h dr c enable control 00b: disable dr c 01b: enable dr c to dac path 10b: disable dr c 11 b: enable drc to adc path update_drc_agc_para m 13 r 1 h update dr c parameter write 1b to update all drc parameter sel_drc_agc_atk 12:8 r/w 2h select drc attack rate (0.375db/tu) ? 00h: 83 usec 01h: 0.167 msec 10h: 5.46 sec others: reserved dr c_agc_rate_sel 7:5 r/w 0h dr c rate control for sample rate change ? 001b: 48khz 010b: 96khz 011b: 192khz 101b: 44.1khz 110b: 88.2khz 111b: 176.4khz others: reserved sel_rc_rate 4:0 r/w 6h select drc recovery rate (0.375db/tu) ? 00h: 83 usec 01h: 0.167 msec 10h: 5.46 sec others: reserved ? attack time=(4*2^n)/sample_rate, n=mx-b4[12:8], default=0.33ms ? recovery time=(4*2^n)/sample_rate, n= mx-b4 [4:0], default=5.3ms ? when change i2s s sample rate, the drc/agc rate control is need to be changed same with i2ss sample rate. when change the drc/agc rate, the parameter of dr c/agc isnt need be modified. when i2ss sample rate is below 48khz, that need to set the dr c/agc rate to 48khz and re-calculate the dr c /a gc s parameter by i2ss sample rate.
alc5672 datasheet 111 rev. 0.75 10.74. mx -b5h: dr c control 4 default: 1f00 h table 90. mx -b5 h: dr c control 4 name bits read/write reset state description alc_drc_ratio_sel2 15:14 r/w 0h drc compression-2 ratio selection 00b: 1:1 01b: 1:2 10b: 1:4 11b : 1:8 sel_ dr c_agc_post_bst 13:8 r/w 1fh dr c digital post-boost gain (0.375db/step) ? 00h= -11.625db 3fh= 12db others: reserved en_dr c_ag c_compres s 7 r/w 0h drc compression function control 0b: disable 1b: enable sel_ratio 6:5 r/w 0h drc compression ratio selection 00b: 1:1 01b: 1:2 10b: 1: 4 11b: 1: 8 alc_noise_gate_drop _en 4 r/w 0h drc noise gate drop mode control 0b: disable 1b: enable reserved 3:2 r 0h reserved noise_gate_ratio_sel 1:0 r/w 0h drc expansion ratio control when noise gate is enabled 00b: 1:1 01b: 2:1 10b: 4:1 11b: 8:1 ? gain table: dec hex boost gain dec hex boost gain dec hex boost gain dec hex boost gain dec hex boost gain 0 0 -11.625 16 10 -5.625 32 20 0.375 48 30 6.375 64 40 1 1 -11.25 17 11 -5.25 33 21 0.75 49 31 6.75 65 41 2 2 -10.875 18 12 -4.875 34 22 1.125 50 32 7.125 66 42 3 3 -10.5 19 13 -4.5 35 23 1.5 51 33 7.5 67 43 4 4 -10.125 20 14 -4.125 36 24 1.875 52 34 7.875 68 44 5 5 -9.75 21 15 -3.75 37 25 2.25 53 35 8.25 69 45 6 6 -9.375 22 16 -3.375 38 26 2.625 54 36 8.625 70 46
alc5672 datasheet 112 rev. 0.75 7 7 -9 23 17 -3 39 27 3 55 37 9 71 47 8 8 -8.625 24 18 -2.625 40 28 3.375 56 38 9.375 72 48 9 9 -8.25 25 19 -2.25 41 29 3.75 57 39 9.75 73 49 10 a -7.875 26 1a -1.875 42 2a 4.125 58 3a 10.125 74 4a 11 b -7.5 27 1b -1.5 43 2b 4.5 59 3b 10.5 75 4b 12 c -7.125 28 1c -1.125 44 2c 4.875 60 3c 10.875 76 4c 13 d -6.75 29 1d -0.75 45 2d 5.25 61 3d 11.25 14 e -6.375 30 1e -0.375 46 2e 5.625 62 3e 11.625 15 f -6 31 1f 0 47 2f 6 63 3f 12 10.75. mx -b6h: dr c control 5 default: 0000 h table 91. mx -b6 h: dr c control 5 name bits read/write reset state description noise_gate_boost 15:12 r/w 0h se lect compensation gain when signal is below noise gate 0h: 0db 1h: 3db 2h: 6db eh: 42db fh: 45db reserved 11:7 r 0h reserved en_drc_agc_noise_ga te 6 r/w 0h enable noise gate function 0b: diaable 1b: enable en_drc_agc_noise_ga te_hold 5 r/w 0h enable noise gate hold data function 0b: disable 1b: enable sel_drc_agc_noise_th 4:0 r/w 0h noise gate threshold (-1.5db/step) 00h: - 24 dbfs 01h: - 25. 5dbfs .. 1fh: - 70 .5 dbfs
alc5672 datasheet 113 rev. 0.75 10.76. mx -b7h: drc control 6 default: 0000 h table 92. mx -b7 h: drc control 6 name bits read/write reset state description reserved 15:12 r 0h reserved alc_thmax2 11:6 r/w 0h drc limiter threshold 2 control (0.75db/step) 00h= 0dbfs 01h= -0.75dbfs 02h= -1.5dbfs 03h= -2.25dbfs .. 1fh= -45dbfs alc_thmax 5:0 r/w 0 h drc limiter threshold control (0.375db/step) 00h= 0dbfs 01h= -0.375dbfs 02h= -0.75dbfs 03h= -1.125dbfs .. 1fh= -23.625dbfs 10.77. mx -bbh: jack detection control 1 default: 0000 h table 93. mx - bb h: jack detection control 1 name bits read/write reset state description sel_gpio_jd1 15:13 r/w 0h gpio jack detect C 1 source selection 000b: off 001b: gpio3 010b: gpio4 011b: gpio5 100b: gpio6 101b: reserved 110b: reserved 111b: reserved reserved 12 r 0h reserved en_jd_hpo 11 r/w 0h enable jack detect trigger hpout 0b: disable 1b: enable polarity_jd_tri_hpo 10 r/w 0h select jack detect polarity trigger hpout 0b: low trigger 1b: high trigger en_jd_spk_l 9 r/w 0h enable jack detect trigger spk_l 0b: disable 1b: enable
alc5672 datasheet 114 rev. 0.75 name bits read/write reset state description polarity_jd_tri_spk_l 8 r/w 0h select jack detect polarity trigger spk_l 0b: low trigger 1b: high trigger en_jd_spk_r 7 r/w 0h enable jack detect trigger spk_r 0b: disable 1b: enable polarity_jd_tri_spk_r 6 r/w 0h select jack detect polarity trigger spk_r 0 b: low trigger 1b: high trigger reserved 5:4 r/w 0h reserved en_jd_lout1 3 r/w 0h enable jack detect trigger lout1 0b: disable 1b: enable polarity_jd_tri_lout1 2 r/w 0h select jack detect polarity trigger lout1 0b: low trigger 1b: high trigger reserved 1:0 r 0h reserved 10.78. mx -bdh: irq control 1 default: 0000 h table 94. mx - bd h: irq control 1 name bits read/write reset state description en_irq_gpio_jd1 15 r/w 0h irq output source configure of gpio jack detection 1 status 0b: bypass 1b: normal en_gpio_jd1_sticky 14 r/w 0h sticky control for gpio jack detect 1 0b: disable 1b: enable inv_gpio_jd1 13 r/w 0h gpio jack detection 1 status polarity 0b: normal 1b: output invert reserved 12:10 r/w 0h reserved en_irq_jd1_1 9 r/w 0h irq output source configure of jd1_1 jack detection status 0b: bypass 1b: normal en_jd1_1_sticky 8 r/w 0h sticky control for jd1_1 jack detect 0b: disable 1b: enable inv_jd1_1 7 r/w 0h jd1_1 jack detection status polarity 0b: normal 1b: output in vert
alc5672 datasheet 115 rev. 0.75 name bits read/write reset state description en_irq_jd1_2 6 r/w 0h irq output source configure of jd1_2 jack detection status 0b: bypass 1b: normal en_jd1_2_sticky 5 r/w 0h sticky control for jd1_2 jack detect 0b: disable 1b: enable inv_jd1_2 4 r/w 0h jd1_2 jack detection status polarity 0b: normal 1b: output invert en_irq_jd2 3 r/w 0h irq output source configure of jd2 jack detection status 0b: bypass 1b: normal en_jd2_sticky 2 r/w 0h sticky control for jd2 jack detect 0b: disable 1b: enable inv_jd2 1 r/w 0h jd2 jack detection status polarity 0b: normal 1b: output invert reserved 0 r 0h reserved 10.79. mx -beh: irq control 2 default: 0000 h table 95. mx - be h: irq control 2 name bits read/write reset state description en_irq_micbias1_ovc d 15 r/w 0h irq output source configure of micbias1 over current status 0b: bypass 1b: normal reserved 14 r/w 0h reserved en_micbias1_ovcd_st icky 13 r/w 0h sticky control for micbias1 over current 0b: disable 1b: enable reserved 12 r/w 0h reserved inv_micbias1_ovcd 11 r/ w 0h micbias1 over current status polarity 0b: normal 1b: output invert reserved 10 r/w 0h reserved sta_micbias1_ovcd 9 r 0h micbias1 over current status read: return status of each status pin write: write 0 to clear stick bit reserved 8:0 r/w 0h reserved
alc5672 datasheet 116 rev. 0.75 10.80. mx -bfh: irq control 3 default: 0000 h ta ble 96. mx -bf h: irq control 3 name bits read/write reset state description reserved 15 r 0h reserved sta_jd2 14 r 0 h status of jd2 jack detection . read: return status of jack detect select output write: write 0 to clear stick bit sta_jd1_2 13 r 0 h status of jd1_2 jack detection . read: return status of jack detect select output write: write 0 to clear stick bit sta_jd1_1 12 r 0 h status of jd1_1 jack detection . read: return status of jack detect select output write: write 0 to clear stick bi t reserved 11 r 0h reserved sta_gpio6 10 r 0h gpio6 pin status read: return status of each gpio pin sta_gpio5 9 r 0h gpio5 pin status read: return status of each gpio pin sta_gpio1 8 r 0h gpio1 pin status read: return status of each gpio pin sta_gpio2 7 r 0h gpio2 pin status read: return status of each gpio pin sta_gpio3 6 r 0h gpio3 pin status read: return status of each gpio pin sta_gpio4 5 r 0h gpio4 pin status read: return status of each gpio pin sta_gpio_jd1 4 r 0 h status of gpio jack detection 1 read: return status of jack detect select output write: write 0 to clear stick bit en_irq_inline 3 r/w 0h irq output source configure of inline command status 0b: bypass 1b: normal sta_inline 2 r 0 h status of inline command trigger read: return status of inline command trigger write: write 0 to clear stick bit en_inline_sticky 1 r/w 0h sticky control for inline command 0b: disable 1b: enable inv_inline 0 r/w 0h inline command status polarity 0b: normal 1b: output invert 10.81. mx-c0h: gpio control 1 default: 00 00 h
alc5672 datasheet 117 rev. 0.75 table 97. mx - c0 h: gpio control 1 name bits read/write reset state description sel_gpio1_type 15 r/w 0h gpio1 pin function select 0b: gpio1 1b: irq output sel_gpio2_type 14 r/w 0h gpio2 pin function select 0b: gpio2 1b: dmic1_scl reserved 13: 9 r/w 0h reserved sel_i2s2_pin 8 r/w 0h i2s-2 pin function selection 0b: i2s function pins 1b: gpio function pins sel_gpio5_type 7 r/w 0h gpio5 pin function select 0b: gpio5 1b: dmic3_sda sel_gpio6_type 6 r/w 0h gpio6 pin function select 0b: gpio6 1b: dmic1_sda reserved 5:0 r/w 0h reserved 10.82. mx -c1h: gpio control 2 default: 0000 h table 98. mx -c1 h: gpio control 2 name bits read/write reset state description reserved 15 r/w 0h reserved sel_gpio5 14 r/w 0h gpio5 pin configuration 0b: input 1b: output sel_gpio5_logic 13 r/w 0h gpio5 output pin control 0b: drive low 1b: drive high inv_gpio5 12 r/w 0h gpio5 pin polarity 0b: normal 1b: output invert sel_gpio4 11 r/w 0h gpio4 pin configuration 0b: input 1b: output sel_gpio4_logic 10 r/w 0h gpio4 output pin control 0b: drive low 1b: drive high inv_gpio4 9 r/w 0h gpio4 pin polarity 0b: normal 1b: output invert sel_gpio3 8 r/w 0h gpio3 pin configuration 0b: input 1b: output
alc5672 datasheet 118 rev. 0.75 name bits read/write reset state description sel_gpio3_logic 7 r/w 0h gpio3 output pin control 0b: drive low 1b: drive high inv_gpio3 6 r/w 0h gpio3 pin polarity 0b: normal 1b: output invert sel_gpio2 5 r/w 0h gpio2 pin configuration 0b: input 1b: output sel_gpio2_logic 4 r/w 0h gpio2 output pin control 0b: drive low 1b: drive high inv_gpio2 3 r/w 0h gpio2 pin polarity 0b: normal 1b: output invert sel_gpio1 2 r/w 0h gpio1 pin configuration 0b: input 1b: output sel_gpio1_logic 1 r/w 0h gpio1 output pin control 0b: drive low 1b: drive high inv_gpio1 0 r/w 0h gpio1 pin polarity 0b: normal 1b: output invert 10.83. mx -c2h: gpio control 3 default: 0000 h table 99. mx -c2 h: gpio control 3 name bits read/write reset state description reserv ed 15:3 r/w 0h reserved sel_gpio6 2 r/w 0h gpio6 pin configuration 0b: input 1b: output sel_gpio6_logic 1 r/w 0h gpio6 output pin control 0b: drive low 1b: drive high inv_gpio6 0 r/w 0h gpio6 pin polarity 0b: normal 1b: output inver t
alc5672 datasheet 119 rev. 0.75 10.84. mx -cfh: sounzreal tm bassback control default: 0013 h table 100 . mx -cf h: sounzreal tm bassback control name bits read/write reset state description en_bb 15 r/w 0h enable bassback function 0b: disable 1b: enable sel_bb_coef 14:12 r/ w 0h select control for bassback coefficient type 000b : type a 001b : type b 010b : type c 011b : type d 1xxb : reserved reserved 11:6 r 0h reserved bb_boost_gain 5:0 r/w 13h select control bassback boost gain 000001b : 1.5db 000010b : 3db 010011 b : 24db 011111b : 42db, with 1.5db/step 10.85. mx -d0h: sounzreal tm trutreble control 1 default: 0680 h table 101. mx - d0 h: sounzreal tm trutreble control 1 name bits read/write reset state description reserved 15:14 r/w 0h reserved en_mp 13 r/w 0h enable trutreble function 0b: disable 1b: enable mp_eg 12:8 r/w 6h trutreble enhanced gain control ? 00000b: -11.625db 00001b: -10.5db . 00110b: - 3db ........... 10100b: 7.5db reserved 7:0 r/w 80h reserved ? eg enhanced gain eg enhanced gain 1 -11.625db 11 2.25 db
alc5672 datasheet 120 rev. 0.75 2 -10.5 db 12 3 db 3 -9 db 13 3.75 db 4 -6.75 db 14 4.5 db 5 -4.5 db 15 4.875 db 6 -3 db 16 5.625 db 7 -1.875 db 17 6 db 8 -0.375 db 18 6.375 db 9 0.375 db 19 7.125 db 10 1.5 db 20 7.5 db 10.86. mx -d1h: sounzreal tm trutreble control 2 default: 1c17 h table 102. mx - d1 h: sounzreal tm l trutreble control 2 name bits read/write reset state description reserved 15:14 r 0h reserved mp_hp_wt 13 r/w 0h select the harmonic weighting 0b: a = 1/4(default) 1b: a = 1/2 m p_og 12:8 r/w 1ch select the origin signal gain 00000b: -5.8125db 00001b: -5.625db 10111b: -0.5625 db ... 11111b: 12db, with 0.1875db/step reserved 7:6 r 0h reserved mp_hg 5:0 r/w 17h select high frequency harmonic gain (0.375 /step) 000000b: -11.625db 000001b: -11.25db 010111b: - 3db ... 111111b: 12db, with 0.375db/step 10.87. mx -d3h: stereo1 adc wind filter control 1 default: a22 0 h table 103. mx -d3 h: stereo1 adc wind filter control 1 name bits read/write reset state description adj_hpf_2 nd _en_stere o1 15 r/w 1h stereo1 adc wind filter enable control 0b : disable and bypass 1b : enable
alc5672 datasheet 121 rev. 0.75 name bits read/write reset state description adj_hpf_coef_l_sel_st ereo1 14:12 r/w 2h stereo1 adc wind filter left channel coefficient coarse selection 000b : fs=8k, fc = 20~2000hz fs=12k, fc = 30~3000hz fs=16k, fc = 40~4000hz 001b : fs=24k, fc = 30~2458hz fs=32k, fc = 40~3278hz 010b : fs=44.1k, fc = 28~1992hz fs=48k, fc = 30~2168hz 011b : fs=88.2k, fc = 28~1869hz fs=96k, fc = 30~2034hz 100b : fs=176.4k, fc = 27~1811hz fs=192k, fc = 30~1971hz others: reserved reserved 11 r 0h reserved adj_hpf_coef_r_sel_st ereo1 10:8 r/w 2h stereo1 adc wind filter right channel coefficient coarse selection 000b : fs=8k, fc = 20~2000hz fs=12k, fc = 30~3000hz fs=16k, fc = 40~4000hz 001b : fs=24k, fc = 30~2458hz fs=32k, fc = 40~3278hz 010b : fs=44.1k, fc = 28~1992hz fs=48k, fc = 30~2168hz 011b : fs=88.2k, fc = 28~1869hz fs=96k, fc = 30~2034hz 100b : fs=176.4k, fc = 27~1811hz fs=192k, fc = 30~1971hz others: reserved reserved 7:0 r/w 20h reserved 10.88. mx -d4h: stereo1 adc wind filter control 2 default: 0000 h table 104. mx -d4 h: stereo1 adc wind filter control 2 name bits read/write reset state description reserved 15:14 r 0 h reserved
alc5672 datasheet 122 rev. 0.75 name bits read/write reset state description adj_hpf_coef_l_num_ stereo1 13:8 r/w 0h stereo1 adc wind filter right channel coefficient fine selection (0~63) reserved 7:6 r 0 h reserved adj_hpf_coef_r_num_ stereo1 5:0 r/w 0h stereo1 adc wind filter left channel coefficient fine selection (0~63) 10.89. mx -d9h: soft volume & zcd control 1 default: 0809 h table 105. mx -d9 h: soft volume & zcd control 1 name bits read/write reset state description en_softvol 15 r/w 0h digital soft volume delay control 0b: disable 1b: enable reserved 14 r /w 0h reserved en_o_svol 13 r /w 0h outvoll/r soft volume delay control 0 b: disable 1 b : enable en_ hp o_ svol 12 r /w 0h hpovoll/r soft volume delay control 0 b : disable 1b: enable en_zcd_digital 11 r/w 1h digital volume zero crossing detection control 0b: disable 1b: enable pow_zcd 10 r /w 0h power on zero crossing 0b: p ower down 1b: power on reserved 9:4 r 0h reserved sel_svol 3:0 r/w 9h soft volume change delay time 0000: 1 svsync 0001: 2 svsync 0010: 4 svsync 0011: 8 svsync 0100: 16 svsync 0101: 32 svsync 0110: 64 svsync 0111: 128 svsync 1000: 256 svsync 1001: 512 svsync 1010: 1024 svsync others: reserved note: svsync=1/fs, step:-1.5dbfs
alc5672 datasheet 123 rev. 0.75 10.90. mx -dah: soft volume & zcd control 2 default: 0000 h table 106. mx -da h: soft volume & zcd control 2 name bits read/write reset state description reserved 15:7 r /w 0h reserved en_zcd_outmixr 6 r /w 0h outmixr zcd control 0 b : disable 1 b : enable en_zcd_outmixl 5 r /w 0h outmixl zcd control 0 b : disable 1 b : enable en_zcd_hpmixr 4 r /w 0h hpmixr zcd control 0 b : disable 1 b : enable en_zcd_hpmixl 3 r /w 0h hpmixl zcd control 0 b : disable 1 b : enable reserved 2 r /w 0h reserved en_zcd_recmixr 1 r /w 0h recmixr zcd control 0 b : disable 1 b : enable en_zcd_recmixl 0 r /w 0h recmixl zcd control 0 b : disable 1 b : enable 10.91. mx -dbh: inline command control 1 default: 0001 h table 107. mx -db h: inline command control 1 name bits read/write reset state description sta_one_up_button 15 r 0h status of one click command for up button write 1 to clear it sta_double_up_button 14 r 0h status of double click command for up button write 1 to clear it sta_hold_up_button 13 r 0h status of hold command for up button write 1 to clear it sta_one_center_butto n 12 r 0h status of one click command for center button write 1 to clear it sta_double_center_bu tton 11 r 0h status of double click command for center button write 1 to clear it sta_hold_center_butto n 10 r 0h status of hold command for center button write 1 to clear it sta_one_down_button 9 r 0h status of one click command for down button write 1 to clear it sta_double_down_but ton 8 r 0h status of double click command for down button write 1 to clear it
alc5672 datasheet 124 rev. 0.75 name bits read/write reset state description sta_hold_down_butto n 7 r 0h status of hold command for down button write 1 to clear it en_inline 6 r /w 0 h enable inline command 0b: disable 1b: enable reserved 5 r 0 h reserved sel_clk_mic 4:3 r/w 0h select inline command debounce clock 00b: osc/2^17 01b: osc/2^16 10b: osc/2^15 11b: osc/2^14 mic_in_det_0_th 2:0 r/w 1h mic input voltage threshold control (cmp0) 000b: 0.09v 001b: 0.12v 010b: 0.15v 011 b: 0.18v 100b: 0.17v 101b: 0.23v 110b: 0.29v 111b: 0.34v 10.92. mx -dch: inline command control 2 default: 0049 h table 108. mx -dc h: inline command control 2 name bits read/write reset state description en_inline_vol 15 r/w 0h enable inline command direct to control digital volume 0b : disable 1 b : enable sel_inline_ctl_if 14 r/w 0h select the inline command control path 0b : if1 dac volume/mute(un-mute) 1 b : if2 dac volume/mute(un-mute) conti_hold_up 13 r/w 0h select hold command behavior for up butt on 0b: one pulse trigger 1b: continue pulse trigger conti_hold_center 12 r/w 0h select hold command behavior for center button 0b: one pulse trigger 1b: continue pulse trigger conti_hold_down 11 r/w 0h select hold command behavior for down button 0 b: one pulse trigger 1b: continue pulse trigger in_det_window 10:0 r/w 49h inline command click window control mx - db[4:3]=00b => (1/osc)*16384*n mx - db[4:3]=01b => (1/osc)*8192*n mx - db[4:3]=10b => (1/osc)*4096*n mx - db[4:3]=11b => (1/osc)*2048*n (n=0~127)
alc5672 datasheet 125 rev. 0.75 10.93. mx -ddh: inline command control 3 default: 0009 h table 109. mx -dd h: inline command control 3 name bits read/write reset state description reserved 15:6 r 0h reserved mic_in_det_1_th 5:3 r/w 1h mic input voltage threshold control (cmp1) 000b: 0.36v 001b: 0.39v 010b: 0.42v 011b: 0.45v 100b: 0.68v 101b: 0.74v 110b: 0.80v 111b: 0.86v mic_in_det_2_th 2:0 r/w 1h mic input voltage threshold control (cmp2) 000b: 0.69v 001b: 0.71v 010b: 0.74v 011b: 0.77v 100b: 1.31v 101b: 1.37v 1 10b: 1.43v 111b: 1.48v 10.94. mx - e0 h: voice dsp control 1 default: 0000 h table 1 10 . mx - e0 h: voice dsp control 1 name bits read/write reset state description aec_cmd 15:8 r/w 0h voice dsp command dsp_clk_sel 7:6 r/w 0h voice dsp control interface clock select 00b: sysclk/3/16 01b: sysclk/4/16 10b: sysclk/6/16 11b: sysclk/8/16
alc5672 datasheet 126 rev. 0.75 name bits read/write reset state description aec_busy 5 r 0h voice dsp r/w busy 0b: normal 1b: busy sel_dsp_cmd 4 r/w 0h voice dsp r/w command 0b: write 1b: read sel_dsp_data_len 3:2 r/w 0h voice dsp control interface data length 00b: 0 byte 01b: 1 byte 10b: 2 byte 11b: 3 byte sel_dsp_addr_len 1 r/w 0h voice dsp control interface address length 0b: 8 bit 1b: 16 bit aec_cmd_start 0 r/w 0h write 1 to start voice dsp control interface command 10.95. mx - e1 h: voice dsp control 2 default: 0000 h table 11 1. mx -e1 h: voice dsp control 2 name bits read/write reset state description aec_addr 15:0 r/w 0h voice dsp address 10.96. mx - e2 h: voice dsp control 3 default: 0000 h table 11 2. mx -e2 h: voice dsp control 3 name bits read/write reset state description aec_write_data 15:0 r/w 0h voice dsp write data 10.97. mx - e3 h: voice dsp control 4 default: 0000 h table 11 3. mx -e3 h: voice dsp control 4 name bits read/write reset state description reserved 15:8 r 0h reserved aec_write_data2 7:0 r/w 0h voice dsp write data
alc5672 datasheet 127 rev. 0.75 10.98. mx - e4 h: voice dsp control 5 default: 0000 h table 11 4. mx -e4 h: voice dsp control 5 name bits read/write reset state description read_data_aec 15:0 r 0h voice dsp read data 10.99. mx - e5 h: voice dsp control 6 default: 0000 h table 11 5. mx -e5 h: voice dsp control 6 name bits read/write reset state description reserved 15:8 r 0h reserved read_data_aec2 7:0 r 0h voice dsp read data 10.100. mx - ec h: mono adc wind filter control 1 default: a200 h table 11 6. mx - ec h: mono adc wind filter control 1 name bits read/write reset state description adj_hpf_2 nd _en_mon o 15 r/w 1h mono adc wind filter enable control 0b : disable and bypass 1b : enable adj_hpf_coef_l_sel_ mono 14:12 r/w 2h mono adc wind filter left channel coefficient coarse selection 000b : fs=8k, fc = 20~2000hz fs=12k, fc = 30~3000hz fs=16k, fc = 40~4000hz 001b : fs=24k, fc = 30~2458hz fs=32k, fc = 40~3278hz 010b : fs=44.1k, fc = 28~1992hz fs=48k, fc = 30~2168hz 011b : fs=88.2k, fc = 28~1869hz fs=96k, fc = 30~2034hz 100b : fs=176.4k, fc = 27~1811hz fs=192k, fc = 30~1971hz others: reserved reserved 11 r 0h reserved
alc5672 datasheet 128 rev. 0.75 name bits read/write reset state description adj_hpf_coef_r_sel_ mono 10:8 r/w 2h mono adc wind filter right channel coefficient coarse selection 000b : fs=8k, fc = 20~2000hz fs=12k, fc = 30~3000hz fs=16k, fc = 40~4000hz 001b : fs=24k, fc = 30~2458hz fs=32k, fc = 40~3278hz 010b : fs=44.1k, fc = 28~1992hz fs=48k, fc = 30~2168hz 011b : fs=88.2k, fc = 28~1869hz fs=96k, fc = 30~2034hz 100b : fs=176.4k, fc = 27~1811hz fs=192k, fc = 30~1971hz others: reserved reserved 7:0 r 0h reserved 10.101. mx -edh: mono adc wind filter control 2 default: 0000 h table 11 7. mx - ed h: mono adc wind filter control 2 name bits read/write reset state description reserved 15:14 r 0 h reserved adj_hpf_coef_l_num_ mono 13:8 r/w 0h mono adc wind filter right channel coefficient fine selection (0~63) reserved 7:6 r 0 h reserved adj_hpf_coef_r_num_ mono 5:0 r/w 0h mono adc wind filter left channel coefficient fine selection (0~63) 10.102. mx - ee h: stereo2 a dc wind filter control 1 default: a200 h table 11 8. mx -ee h: stereo2 adc wind filter control 1 name bits read/write reset state description adj_hpf_2 nd _en_stere o2 15 r/w 1h stereo2 adc wind filter enable control 0b : disable and bypass 1b : enable
alc5672 datasheet 129 rev. 0.75 name bits read/write reset state description adj_hpf_coef_l_sel_ st ereo2 14:12 r/w 2h stereo2 adc wind filter left channel coefficient coarse selection 000b : fs=8k, fc = 20~2000hz fs=12k, fc = 30~3000hz fs=16k, fc = 40~4000hz 001b : fs=24k, fc = 30~2458hz fs=32k, fc = 40~3278hz 010b : fs=44.1k, fc = 28~1992hz fs=48k, fc = 30~2168hz 011b : fs=88.2k, fc = 28~1869hz fs=96k, fc = 30~2034hz 100b : fs=176.4k, fc = 27~1811hz fs=192k, fc = 30~1971hz others: reserved reserved 11 r 0h reserved adj_hpf_coef_r_sel_ st ereo2 10:8 r/w 2h stereo2 adc wind filter right channel coefficient coarse selection 000b : fs=8k, fc = 20~2000hz fs=12k, fc = 30~3000hz fs=16k, fc = 40~4000hz 001b : fs=24k, fc = 30~2458hz fs=32k, fc = 40~3278hz 010b : fs=44.1k, fc = 28~1992hz fs=48k, fc = 30~2168hz 011b : fs=88.2k, fc = 28~1869hz fs=96k, fc = 30~2034hz 100b : fs=176.4k, fc = 27~1811hz fs=192k, fc = 30~1971hz others: reserved reserved 7:0 r 0h reserved
alc5672 datasheet 130 rev. 0.75 10.103. mx -efh: stereo2 adc wind filter control 2 default: 0000 h table 11 9. mx -ef h: stereo2 adc wind filter control 2 name bits read/write reset state description reserved 15:14 r 0 h reserved adj_hpf_coef_l_num_ stereo2 13:8 r/w 0h stereo2 adc wind filter right channel coefficient fine selection (0~63) reserved 7:6 r 0 h reserved adj_hpf_coef_r_num_ stereo2 5:0 r/w 0h stereo2 adc wind filter left channel coefficient fine selection (0~63) 10.104. mx - f8 h: jack detection control default: 0000 h table 1 20 . mx - f8h: jack detection control name bits read/write reset state description reserved 15:8 r 0h reserv ed en_jd_combo_jack 7 r/w 0h enable jack detect to trigger combo jack 0b: disable 1b: enable polarity_jd_tri_cbj 6 r/w 0h select jack detect polarity to trigger combo jack 0b: low trigger 1b: high trigger sel_jd_trigger_cbj 5:3 r/w 0h jd trigger source selection for combo jack 000b: from sta_gpio_jd1 001b: from sta_jd1_1 010b: from sta_jd1_2 011b: from sta_jd2 100b: reserved 101b: reserved 110b: from mx0b[12] others: reserved sel_jd_trigger_hpo 2:0 r/w 0h jd trigger source selection for h po 000b: from sta_gpio_jd1 001b: from sta_jd1_1 010b: from sta_jd1_2 011b: from sta_jd2 100b: reserved 101b: reserved others: reserved
alc5672 datasheet 131 rev. 0.75 10.105. mx - f9 h: jack detection control default: 0000 h table 121. mx - f9h: jack detection control name bits read/write reset state description reserved 15:12 r 0h reserved sel_jd_trigger_spk 11:9 r/w 0h jd trigger source selection for spk_out 000b: from sta_gpio_jd1 001b: from sta_jd1_1 010b: from sta_jd1_2 011b: from sta_jd2 100b: reserved 10 1b: reserved others: reserved reserved 8:6 r 0h reserved sel_jd_trigger_lout1 5:3 r/w 0h jd trigger source selection for lout1 000b: from sta_gpio_jd1 001b: from sta_jd1_1 010b: from sta_jd1_2 011b: from sta_jd2 100b: reserved 101b: reserved others: reserved reserved 2:0 r/w 0h reserved 10.106. mx -fah: general control 1 default: 8010 h table 122. mx - fa h: general control 1 name bits read/write reset state description reserved 15:14 r/w 2 h reserved rst_dsp 13 r/w 0h voice dsp reset control 0b: normal 1b: reset sel_if1_adc1_data_in 1 12 r/w 0h selection-1 for if1 adc1 input data 0b: if_adc1 1b: if_adc3 sel_if1_adc1_data_in 2 11 r/w 0h selection-2 for if1 adc1 input data 0b: if_adc1 or if1_adc3 1b: txdp_adc sel_if1_adc2_data_in 1 10 r/w 0h selection for if1 adc2 input data 0b: if_adc2 1b: txdp_adc reserved 9 :4 r/w 1 h reserved
alc5672 datasheet 132 rev. 0.75 name bits read/write reset state description en_detect_clk_sys 3 r/w 0h enable mclk detection and auto switch to rc clock when mclk is remove 0b: disable 1b: enable reserved 2 :1 r 0h reserved digital_gate_ctrl 0 r /w 0h enable mclk g at ing control 0b: disable 1b: enable 10.107. mx -fbh: general control 2 default: 0033 h table 123. mx -fb h: general control 2 name bits read/write reset state description reserved 15:11 r/w 0 h reserved sel_pow_capless 10 r/w 0h headphone capless power control 0b: controlled by combo jack function 1b: controlled by register (mx -8eh) en_sel_in1_p 9 r/w 0h in1p input path control 0b: disable 1b: enable en_sel_in1_n 8 r/w 0h in1n input path control 0b: disable 1b: enable reserved 7:5 r/w 1h reserved hp_depop_ctrl 4 r/w 1h headphone de-pop mode control 0b: disable 1b: enable reserved 3:0 r/w 3h reserved 10.108. pr -3dh: adc/dac reset control default: 2808 h table 124. pr - 3d h: adc/dac reset control name bits read/write reset state description reserved 15:13 r/w 1h reserved en_ckgen_adc 12 r/w 0h enable adc clock generator 0b: disable 1b: enable reserved 11 r/w 1 h reserved ckxen_dac 10 r/w 0h enable chopper function of dac 0b: disable 1b: enable
alc5672 datasheet 133 rev. 0.75 name bits read/write reset state description en_ckgen_dac 9 r/w 0h enable dac clock generator 0b: disable 1b: enable en_psv_dac 8 r/w 0h enable power saving mode of dac 0b: disable 1b: enable reserved 7 :0 r/w 8 h reserved 10.109. pr -a4h: dac_l eq (lpf:a1) default: 1c10 h table 125. pr -a4 h: dac_l eq (lpf2:a1) name bits read/write reset state description lpf_ a1 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99) 10.110. pr -a5h: dac_l eq (lpf:h0) default: 01f4 h table 126. pr -a5 h: dac_l eq (lpf2:h0) name bits read/write re set state description lpf_h0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.111. pr -a6h: dac_r eq (lpf:a1) default: 1c10 h table 127. pr -a6 h: dac_r eq (lpf2:a1) name bits read/write reset state des cription lpf_ a1 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99)
alc5672 datasheet 134 rev. 0.75 10.112. pr -a7h: dac_r eq (lpf:h0) default: 01f4 h table 128. pr -a7 h: dac_r eq (lpf:h0) name bits read/write reset state description lp f_h0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.113. pr -aeh: dac_l eq (bpf2:a1) default: c882 h table 129. pr -ae h: dac_l eq (bpf2:a1) name bits read/write reset state description b pf 2_ a1 15:0 r /w c882 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99) 10.114. pr -afh: dac_l eq (bpf2:a2) default: 1c10 h table 1 30 . pr -af h: dac_l eq (bpf2:a2) name bits read/write reset state description b pf 2_ a2 15:0 r/w 1c10 h 2 s complement in 3.13 format. (the range is from C 4~3.99, the a2 should be in -2 ~ 1.99) 10.115. pr - b0 h: dac_l eq (bpf2:h0) default: 01f4 h table 131. pr - b0 h: dac_l eq (bpf2:h0) name bits read/write reset state description b pf 2_ h0 15:0 r/w 01f4 h 2s compleme nt in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99)
alc5672 datasheet 135 rev. 0.75 10.116. pr - b1 h: dac_r eq (bpf2:a1) default: c882 h table 13 2. pr - b1 h: dac_r eq (bpf2:a1) name bits read/write reset state description b pf 2_ a1 15:0 r/w c882 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99) 10.117. pr - b2 h: dac_r eq (bpf2:a2) default: 1c10 h table 13 3. pr - b2 h: dac_r eq (bpf2:a2) name bits read/write reset state description b pf 2_ a2 15:0 r/w 1c10 h 2s complement in 3.13 format. (t he range is from C 4~3.99, the a2 should be in -2 ~ 1.99) 10.118. pr - b3 h: dac_r eq (bpf2:h0) default: 01f4 h table 13 4. pr - b3 h: dac_r eq (bpf2:h0) name bits read/write reset state description b pf 2_ h0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.119. pr - b4 h: dac_l eq (bpf3:a1) default: e904 h table 13 5. pr - b4 h: dac_l eq (bpf3:a1) name bits read/write reset state description b pf 3_ a1 15:0 r/w e904 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99)
alc5672 datasheet 136 rev. 0.75 10.120. pr - b5 h: dac_l eq (bpf3:a2) default: 1c10 h table 13 6. pr - b5 h: dac_l eq (bpf3:a2) name bits read/write reset state description b pf 3_ a2 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a2 should be in -2 ~ 1.99) 10.121. pr - b6 h: dac_l eq (bpf3:h0) default: 01f4 h table 137. pr - b6 h: dac_l eq (bpf3:h0) name bits read/write reset state description b pf 3_ h0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.122. pr - b7 h: dac_r eq (bpf3:a1) default: e904 h table 13 8. pr - b7 h: dac_r eq (bpf3:a1) name bits read/write reset state description b pf 3_ a1 15:0 r/w e904 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1 .9 9) 10.123. pr - b8 h: dac_r eq (bpf3:a2) default: 1c10 h table 13 9. pr - b8 h: dac_r eq (bpf3:a2) name bits read/write reset state description b pf 3_ a2 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a2 should be in -2 ~ 1.99)
alc5672 datasheet 137 rev. 0.75 10.124. pr - b9 h: dac_r eq (bpf3:h0) default: 01f4 h table 1 40 . pr - b9 h: dac_r eq (bpf3:h0) name bits read/write reset state description b pf 3_ h0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.125. pr -bah: dac_l eq (bpf4:a1) default: e904 h table 141. pr - ba h: dac_l eq (bpf4:a1) name bits read/write reset state description b pf 4_ a1 15:0 r/w e904 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99) 10.126. pr - bb h: dac_l eq (bpf4:a 2) default: 1c10 h table 142. pr - bb h: dac_l eq (bpf4:a2) name bits read/write reset state description b pf 4_ a2 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a2 should be in -2 ~ 1.99) 10.127. pr - bc h: dac_l eq (bpf4:h0) default: 01f4 h table 143. pr - bc h: dac_l eq (bpf4:h0) name bits read/write reset state description b pf 4_ h0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99)
alc5672 datasheet 138 rev. 0.75 10.128. pr -bdh: dac_r eq (bpf4:a1) default: e904 h ta ble 14 4. pr - bd h: dac_r eq (bpf4:a1) name bits read/write reset state description b pf 4_ a1 15:0 r/w e904 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99) 10.129. pr - be h: dac_r eq (bpf4:a2) default: 1c10 h table 14 5. pr-be h: dac_r eq (bpf4:a2) name bits read/write reset state description b pf 4_ a2 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a2 should be in -2 ~ 1.99) 10.130. pr - bf h: dac_r eq (bpf4:h0) default: 01f4 h table 14 6. pr - bf h: dac_r eq (bpf4:h0) name bits read/write reset state description b pf 4_ h0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.131. pr - c0 h: dac_l eq (hpf1:a1) default: 1c10 h table 147. pr - c0 h: dac_l eq (h pf 1:a1) name bits read/write reset state description h pf 1_a1 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99)
alc5672 datasheet 139 rev. 0.75 10.132. pr - c1 h: dac_l eq (h pf 1:h0) default: 01f4 h table 148. pr - c1 h: dac_l eq (h pf 1:h0) name bits read/write reset state description h pf 1_ h0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.133. pr - c2 h: dac_r eq (hpf1:a1) default: 1c10 h table 14 9. pr - c2 h: dac_r eq (hpf1:a1) name bits read/write reset state description h pf 1_ a1 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99) 10.134. pr - c3 h: dac_r eq (hpf1:h0) default: 01f4 h table 1 50 . pr - c3 h: dac_r eq (hpf1:h0) name bits read/write reset state description h pf 1_ h0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.135. pr - c4 h: dac_l eq (hpf2:a1) default: 2000 h table 151. pr - c4 h: dac_l eq (hpf2:a1) name bits read/write reset state description h pf 2_ a1 15:0 r/w 2000 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99)
alc5672 datasheet 140 rev. 0.75 10.136. pr - c5 h: dac_l eq (hpf2:a2) default: 0000 h table 152. pr - c5 h: dac_l eq (hpf2:a2) name bits read/write reset state description hpf2_ a2 15:0 r/w 0000 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a2 should be in -2 ~ 1.99) 10.137. pr - c6 h: dac_l eq (hpf2:h0) default: 1ff1 h table 153. pr - c6 h: dac_l eq (h pf 2:h0) name bits read/write reset state description h pf 2_ h0 15:0 r/w 1ff1 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.138. pr - c7 h: dac_r eq (hpf2:a1) default: 2000 h table 154. pr - c7 h: dac_r eq (hpf2:a1) name bits read/write reset state description h pf 2_ a1 15:0 r/w 2000 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99) 10.139. pr - c8 h: dac_r eq (hpf2:a2) default: 0000 h table 155. pr - c8 h: dac_r eq (hpf2:a2) name bits read/write reset state description h pf 2_ a2 15:0 r/w 0000 h 2s complem ent in 3.13 format. (the range is from C 4~3.99, the a2 should be in -2 ~ 1.99)
alc5672 datasheet 141 rev. 0.75 10.140. pr - c9 h: dac_r eq (hpf2:h0) default: 1ff1 h table 156. pr -c9 h: dac_r eq (hpf2:h0) name bits read/write reset state description h pf 2_ h0 15:0 r/w 1ff1 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.141. pr - ca h: dac_l eq pre-volume control default: 0800 h table 157. pr -ca h: dac_l eq pre-volume control name bits read/write reset state description da_eq_pre_vol_l 15:0 r/w 0800h dac left channel eq pre-volume control 2s complement in 5.11 format. (default is 0db) the range is from -16 ~ 15.99, pre-gain should be in 0 ~ 15.99 [+24db ~ -66db] 10.142. pr - cb h: dac_r eq pre-volume control default: 0800 h table 158. pr -cb h: dac_r eq pre-volume control name bits read/write reset state description da_eq_pre_vol_l 15:0 r/w 0800h dac right channel eq pre-volume control 2s complement in 5.11 format. (default is 0db) the range is from -16 ~ 15.99, pre-gain should be in 0 ~ 15.99 [+24db ~ -66db]
alc5672 datasheet 142 rev. 0.75 10.143. pr- cc h: dac_l eq post-volume control default: 0800 h table 159. pr -cc h: dac_l eq post-volume control name bits read/write reset state description da_eq_post_vol_l 15:0 r/w 0800h dac left channel eq post-volume control 2s complement in 5.11 format. (defa ult is 0db) the range is from -16 ~ 15.99, pre-gain should be in 0 ~ 15.99 [+24db ~ -66db] 10.144. pr - cd h: dac_r eq post-volume control default: 0800 h table 1 60 . pr -cd h: dac_r eq post-volume control name bits read/write reset state description da_eq_post_vol_l 15:0 r/w 0800h dac right channel eq post-volume control 2s complement in 5.11 format. (default is 0db) the range is from -16 ~ 15.99, pre-gain should be in 0 ~ 15.99 [+24db ~ -66db] 10.145. pr - ce h: adc eq (lpf:a1) default: 1c10 h table 161. pr -ce h: ad c eq (lpf:a1) name bits read/write reset state description ad_eq_lpf_a1 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99)
alc5672 datasheet 143 rev. 0.75 10.146. pr - cf h: adc eq (lpf:h0) default: 01f4 h table 162. pr -cf h: ad c eq (lpf:h0) na me bits read/write reset state description ad_eq_lpf_h0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.147. pr - d0 h: adc eq (bpf1:a1) default: e904 h table 163. pr - d0 h: ad c eq (bpf1:a1) name bits rea d/write reset state description ad_eq_bpf1_a1 15:0 r/w e904 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99) 10.148. pr - d1 h: adc eq (bpf1:a2) default: 1c10 h table 164. pr -d1 h: ad c eq (bpf1:a2) name bits read/write re set state description ad_eq_bpf1_a2 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a2 should be in -2 ~ 1.99) 10.149. pr - d2 h: adc eq (bpf1:h0) default: 01f4 h table 165. pr -d2 h: ad c eq (bpf1:h0) name bits read/write reset state description ad_eq_bpf1 _h 0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99)
alc5672 datasheet 144 rev. 0.75 10.150. pr - d3 h: adc eq (bpf2:a1) default: e904 h table 166. pr -d3 h: ad c eq (bpf2:a1) name bits read/write reset state description ad_eq_bpf2_a1 15:0 r/w e904 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99) 10.151. pr - d4 h: adc eq (bpf2:a2) default: 1c10 h table 167. pr -d4 h: ad c eq (bpf2:a2) name bits read/write reset state description ad_eq_b pf 2_a2 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a2 should be in -2 ~ 1.99) 10.152. pr - d5 h: adc eq (bpf2:h0) default: 01f4 h table 168. pr -d5 h: ad c eq (bpf2:h0) name bits read/write reset state description ad_eq_bpf2 _h 0 15: 0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.153. pr - d6 h: adc eq (bpf3:a1) default: e904 h table 169. pr -d6 h: ad c eq (bpf3:a1) name bits read/write reset state description ad_eq_bpf3_a1 15:0 r/w e904 h 2s complement in 3.13 format. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99)
alc5672 datasheet 145 rev. 0.75 10.154. pr - d7 h: adc eq (bpf3:a2) default: 1c10 h table 1 70 . pr -d7 h: ad c eq (bpf3:a2) name bits read/write reset state description ad_eq_bpf3_a2 15:0 r/w 1c10 h 2s com plement in 3.13 format. (the range is from C 4~3.99, the a2 should be in -2 ~ 1.99) 10.155. pr - d8 h: adc eq (bpf3:h0) default: 01f4 h table 171. pr -d8 h: ad c eq (bpf3:h0) name bits read/write reset state description ad_eq_bpf3 _h 0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.156. pr - d9 h: adc eq (bpf4:a1) default: e904 h table 172. pr -d9 h: ad c eq (bpf4:a1) name bits read/write reset state description ad_eq_bpf4_a1 15:0 r/w e904 h 2s complement in 3.13 form at. (the range is from C 4~3.99, the a1 should be in -2 ~ 1.99) 10.157. pr - da h: adc eq (bpf4:a2) default: 1c10 h table 173. pr -da h: ad c eq (bpf4:a2) name bits read/write reset state description ad_eq_bpf4_a2 15:0 r/w 1c10 h 2s complement in 3.13 format. (the r ange is from C 4~3.99, the a2 should be in -2 ~ 1.99)
alc5672 datasheet 146 rev. 0.75 10.158. pr - db h: adc eq (bpf4:h0) default: 01f4 h table 174. pr -db h: ad c eq (bpf4:h0) name bits read/write reset state description ad_eq_bpf4 _h 0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is fr om C 4~3.99, the h0 should be in -4 ~ 3.99) 10.159. pr - dc h: adc eq (hpf1:a1) default: 1c10 h table 175. pr -dc h: ad c eq (hpf1:a1) name bits read/write reset state description ad_eq_hpf1_a1 15:0 r/w 1c10 h 2s complement in 3.13 format. (the range is from C 4~3.99 , the a1 should be in -2 ~ 1.99) 10.160. pr - dd h: adc eq (hpf1:h0) default: 01f4 h table 176. pr -dd h: ad c eq (hpf1:h0) name bits read/write reset state description ad_eq_hpf1_h0 15:0 r/w 01f4 h 2s complement in 3.13 format. (the range is from C 4~3.99, the h0 should be in -4 ~ 3.99) 10.161. pr - e1 h: adc eq pre-volume control default: 0800 h table 177. pr - e1 h: ad c eq pre-volume control name bits read/write reset state description ad_eq_pre_vol 15:0 r/w 0800h adc left channel eq pre-volume control 2s complement in 5. 11 format. (default is 0db) the range is from -16 ~ 15.99, pre-gain should be in 0 ~ 15.99 [+24db ~ -66db]
alc5672 datasheet 147 rev. 0.75 10.162. pr - e2 h: adc eq post-volume control default: 0800 h table 178. pr -e2 h: ad c eq post-volume control name bits read/write reset state description ad_eq_post_vol 15:0 r/w 0800h adc left channel eq post-volume control 2s complement in 5.11 format. (default is 0db) the range is from -16 ~ 15.99, pre-gain should be in 0 ~ 15.99 [+24db ~ -66db] 10.163. pr - e5 h: dac_l biquad eq (bpf1:h0-1) default: 0000 h table 179. pr -e5 h: da c _l biquad eq (bpf1:h0- 1) name bits read/write reset state description reserved 15:13 r 0h reserved eq_biquad_h0_l_msb 12 :0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.164. pr - e6 h: dac_l biquad eq (bpf1:h0-2) default: 0000 h table 1 80 . pr -e6 h: da c _l biquad eq (bpf1:h0-2) name bits read/write reset state description eq_biquad_h0_l_lsb 15:0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.165. pr - e7 h: dac_l biquad eq (bpf1:b1-1) default: 0000 h table 181. pr -e7 h: da c _l biquad eq (bpf1:b1- 1) name bits read/write reset state description reserved 15:13 r 0h reserved eq_biquad_b1_l_msb 12 :0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99)
alc5672 datasheet 148 rev. 0.75 10.166. pr - e8 h: dac_l biquad eq (bpf1:b1-2) default: 000 0 h table 182. pr -e8 h: da c _l biquad eq (bpf1:b1- 2) name bits read/write reset state description eq_biquad_b1_l_lsb 15:0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.167. pr - e9 h: dac_l biquad eq (bpf1:b2-1) default: 0000 h table 183. pr-e9 h: da c _l biquad eq (bpf1:b2- 1) name bits read/write reset state description reserved 15:13 r 0h reserved eq_biquad_b2_l_msb 12 :0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.168. pr - ea h: dac_l biquad eq (bpf1:b2-2) default: 0000 h table 184. pr -ea h: da c _l biquad eq (bpf1:b2- 2) name bits read/write reset state description eq_biquad_b2_l_lsb 15:0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.169. pr - eb h: dac_l biquad eq (bpf1:a1-1) default: 0000 h table 185. pr -eb h: da c _l biquad eq (bpf1:a1- 1) name bits read/write reset state description reserved 15:13 r 0h reserved eq_biquad_a1_l_msb 12 :0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99)
alc5672 datasheet 149 rev. 0.75 10.170. pr - ec h: dac_l biquad eq (bpf1:a1-2) default: 0000 h table 186. pr -ec h: da c _l biquad eq (bpf1:a1- 2) name bits read/write reset state description eq_biquad_a1_l_lsb 15:0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.171. pr - ed h: dac_l biquad eq (bpf1:a2-1) default: 0000 h table 187. pr -ed h: da c _l biquad eq (bpf1:a2- 1) name bits read/write reset state description reserved 15:13 r 0h reserved eq_biquad_a2_l_msb 12 :0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.172. pr - ee h: dac_l biquad eq (bpf1:a2-2) default: 0000 h tab le 188. pr -ee h: da c _l biquad eq (bpf1:a2- 2) name bits read/write reset state description eq_biquad_a2_l_lsb 15:0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.173. pr - ef h: dac_r biquad eq (bpf1:h0-1) default: 0000 h table 189. pr -ef h: da c _r biquad eq (bpf1:h0- 1) name bits read/write reset state description reserved 15:13 r 0h reserved eq_biquad_h0_r_msb 12 :0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99)
alc5672 datasheet 150 rev. 0.75 10.174. pr - f0 h: dac_r biquad eq (bpf1:h0-2) default: 0000 h tab le 190. pr - f0h: da c _r biquad eq (bpf1:h0- 2) name bits read/write reset state description eq_biquad_h0_r_lsb 15:0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.175. pr - f1 h: dac_r biquad eq (bpf1:b1-1) default: 0000 h table 1 91 . pr - f1h: da c _r biquad eq (bpf1:b1- 1) name bits read/write reset state description reserved 15:13 r 0h reserved eq_biquad_b1_r_msb 12 :0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.176. pr - f2 h: dac_r biquad eq (bpf1:b1-2) default: 0000 h table 192. pr - f2h: da c_r biquad eq (bpf1:b1- 2) name bits read/write reset state description eq_biquad_b1_r_lsb 15:0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.177. pr - f3 h: dac_ r biquad eq (bpf1:b2-1) default: 0000 h table 193. pr - f3h: da c_r biquad eq (bpf1:b2- 1) name bits read/write reset state description reserved 15:13 r 0h reserved eq_biquad_b2 _r _msb 12 :0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99)
alc5672 datasheet 151 rev. 0.75 10.178. pr - f4 h: dac_ r biquad eq (bpf1:b2-2) default: 0000 h table 194. pr - f4h: da c_r biquad eq (bpf1:b2- 2) name bits read/write reset state description eq_biquad_b2 _r _lsb 15:0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.179. pr - f5 h: dac_ r biquad eq (bpf1:a1-1) default: 0000 h table 195. pr - f5h: da c_r biquad eq (bpf1:a1- 1) name bits read/write reset state description reserved 15:13 r 0h reserved eq_biquad_a1_r_msb 12 :0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.180. pr - f6 h: dac_ r biquad eq (bpf1:a1-2) default: 0000 h table 196. pr - f6h: da c_r biquad eq (bpf1:a1- 2) name bits read/write reset state description eq_biquad_a1 _r _lsb 15:0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.181. pr - f7 h: dac_ r biquad eq (bpf1:a2-1) default: 0000 h table 197. pr - f7h: da c_r biquad eq (bpf1:a2- 1) name bits read/write reset state description reserved 15:13 r 0h reserved eq_biquad_a2_r_msb 12 :0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99)
alc5672 datasheet 152 rev. 0.75 10.182. pr - f8 h: dac_ r biquad eq (bpf1:a2-2) default: 0000 h table 198. pr - f8h: da c_r biquad eq (bpf1:a2- 2) name bits read/write reset state description eq_biquad_a2 _r _lsb 15:0 r/w 0 h 2s complement in 4. 25 format. (the range is from C 8~7.99) 10.183. mx -feh: vendor id default: 10ec h table 199. mx - feh: vendor id name bits read/write reset state description vendor_id 15:0 r 10ec h vendor id
alc5672 datasheet 153 rev. 0.75 11. electrical characteristics 11.1. dc characteristics 11.1.1. absolute maximum ratings table 200 . absolute maximum ratings parameter symbol min typ max units power supplies digital io buffer digital core analog headphone micbias speaker db vdd dc vdd avdd cpvdd micvdd spkvdd -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 - - - - - - 3.63 1.4 1.98 1.98 3.63 7 1 v v v v v v operating ambient temperature ta - 25 - +85 o c storage temperature ts - 55 - +125 o c note 1: spkvdd=5v with 3.5% duty cycle power bouncing up to spkvdd=7v is acceptable. 11.1.2. recommended operating conditions table 20 1. recommended operating conditions parameter symbol min typ max units digital io buffer db vdd 1.71 1.8 3. 6 v digital core dcv dd 1.05 1.2 1.3 v analog avdd 1.71 1.8 1.9 v analog dacref 1.71 1.8 1.9 v headphone cpvdd 1.71 1.8 1.9 v micbias micvdd 3.0 3.3 3. 6 v speaker spkvdd 1 3.0 3. 6/5.0 5 .5 v note 1: a 10f capacitor must be connected from spkvdd to spkgnd, and should b e placed as close as possible to the spkvdd pin. 11.1.3. static characteristics table 20 2. static characteristics parameter symbol min typ max units input voltage range v in -0.30 - dbvdd+0.30 v low level input voltage v il - - 0.35db vdd v high level input voltage v ih 0.65db vdd - - v high level output voltage v oh 0.9db vdd - - v low level output voltage v ol - - 0.1db vdd v output buffer high drive current - - 15 - ma output buffer low drive current - - 14.7 - ma input buffer pull-up resistor - 125 148 18 0 k ? i np ut buffer pull-down resistor - 19 3 225 266 k ? note: db vdd= 1.8 v, dcvdd=1.2v, t ambient = 40 ? c.
alc5672 datasheet 154 rev. 0.75 11.2. analog performance characteristics table 20 3. analog performance characteristics parameter min typ max units full scale input voltage line inputs (single-ended) mic inputs (single-ended ) mic inputs (differential) - - - 0. 6 0. 6 1.2 - - - vrms vrms vrms full scale output voltage line outputs (single-ended) line outputs (differential) headphone amplifiers outputs (for 10kohm load) headphone amplifiers outputs (for 16ohm load) headphone amplifiers outputs (for 32ohm load) speaker amplifiers outputs (spkvdd=5.0v with 4 ? load, 1% thd+n) - - - - - - 1.0 1.0 1.0 0.9 1.0 2.9 - - - - - - vrms vrms vrms vrms vrms vrms s/n ratio stereo dac direct to hp_l/r with 1 6/32 /10kohm stereo dac direct to spk_out with 8ohm/5v (differential) line_in to stereo adc with 0db (single-end) mic_in to stereo adc with 0db (differential or single-end) mic_in to stereo adc with 20db and micbias (differential or single-end) mic_in to stereo adc with 40db and micbias (differential or single-end) mic_in to stereo adc with 50db and micbias (differential or single-end) - - 100 93 93 93 85 72 65 102 95 95 db a dba dba dba dba dba dba total harmonic distortion + noise dac direct to hp_l/r with 16ohm po = 20mw/ch (16ohm) (with aes17 filter) po = 20mw/ch (32ohm) (with aes17 filter) dac direct to hp_l/r with 10kohm -3dbfs dac direct to spk_out (differential) po=1 .2 w (5v/8ohm) po=2.1w (5v/4ohm) po=920mw (4.2v/8ohm) po=650mw (3.6v/8ohm) line_in to stereo adc with 0db (single-end) mic_in to stereo adc with 0db (differential or single-end) mic_in to stereo adc with 20db and micbias (differential or single-end) mic_in to stereo adc with 40db and micbias (differential or - 81 - 81 -85 <1 <1 <1 <1 - 84 - 84 - 82 - 68 - 83 - 83 db db db % % % % db db db db
alc5672 datasheet 155 rev. 0.75 parameter min typ max units single-end) mic_in to stereo adc with 50db and micbias (differential or single-end) - 60 db btl speaker amplifier efficiency (f in =1khz, 8 ? load, spkvdd=5.0v, output power=1.5w, with lc filter, l=33uh and c=1uf) class-d (stereo mode) - 89 - % power consumption (slave i2s mode, 16 -bit, sr: 44.1khz) p_power down (no clock input) p_playback (stereo dac to hp_out with 16 ohm load, with clock, play silence) p_playba ck (stereo dac to hp_out with 16 ohm load, with clock, po=1mw/ch) p_record (line_in to stereo adc, with clock) < 60 <= 5 .5 <= 13 < 10 uw mw mw mw power down current i dda (analog block) i ddd (digital block) - - - - 10 30 a a micbias1 output voltage setting 1 setting 2 - - 0.9*micvdd 0.75*micvdd - - v v micbias1 drive current micbias = 0.9*ldo2_o - 4 - ma note: standard test conditions: t ambient =25 ? c db vdd= 1.8v dcvdd=1.2v avdd=1.8v micvdd=3.3v cpvdd=1.8v spkvdd=5.0v or 4.2v or 3.6v. 1khz input sine wave; pcm sampling frequency=48khz; test bench characterization bw: 10hz~22khz, 0db attenuation dba: with a-weighting
alc5672 datasheet 156 rev. 0.75 11.3. signal timing 11.3.1. i 2 c control interface t h (5) t w (9) t w (10) t h (6) t su (7) t sp t su (8) sclk sda figure 33. i 2 c control interface table 20 4. i 2 c timing parameter symbol min typ max units clock pulse duration t w (9) 1.3 - - s clock pulse duration t w (10) 600 - - ns clock frequency f 0 - 400k hz start hold time t h (5) 600 - - ns data setup time t su (7) 100 - - ns data hold time t h (6) - - 900 ns rising time t r - - 300 ns falling time t f - - 300 ns stop setup time t su (8) 600 - - ns pulse width of spikes suppressed input filter t sp 0 - 50 ns
alc5672 datasheet 157 rev. 0.75 11.3.2. i 2 s/pcm interface master mode figure 34. timing of i 2 s/pcm master mode table 20 5. timing of i 2 s/pcm master mode parameter symbol min typ max units lrck output to bclk delay t lrd - - 30 ns data output to bclk delay t add - - 30 ns data input setup time t das 10 - - ns data input hold time t dah 10 - - ns
alc5672 datasheet 158 rev. 0.75 11.3.3. i 2 s/pcm interface slave mode figure 35. i 2 s/pcm slave mode timing table 20 6. i 2 s/pcm slave mode timing parameter symbol min typ max units bclk high pulse width t bch 20 - - ns bclk low pulse width t bcl 20 - - ns lrck input setup time t lrs 30 - - ns data output to bclk delay t add - - 30 ns data input setup time t das 10 - - ns data input hold time t dah 10 - - ns
alc5672 datasheet 159 rev. 0.75 11.3.4. digital microphone interface t das t dah left data right data left data clock output data input t clkout t das t dah figure 36. digital microphone interface timing table 20 7. digital microphone interface timing parameter symbol min typ max units clock output rate t clkout 300 - - ns clock duty cycle 45:55 55:45 data input setup time t das 20 - - ns data input hold time t dah 10 - - ns
alc5672 datasheet 160 rev. 0.75 12. application circuits spo_rn r13 0/5% c12 2.2uf/6.3v cpvee r14 0/5% r26 10k/5% gpio1/irq 1.71v ~ 1.9v loutl c21 0.1uf/6.3v c22 4.7uf/6.3v cpvdd spkvdd c29 0.1uf/6.3v dbvdd u1 alc5672 spo_lp 1 loutl 28 loutr 29 micbias1 13 dacref 7 spo_ln 48 spkvddl 47 scl 39 avdd 6 dacdat1 34 adcdat1 35 gpio2/dmic_scl 42 dcvdd 3 dbvdd 2 agnd 10 dacdat2 32 cpn1 23 cpvee 27 hpo_l 18 bclk1 37 lrck1 36 cpvdd 21 cpp1 22 micbias2 9 hpo_r 19 sda 40 mclk 38 spo_rp 45 in1p_ring2 11 in2p 4 vref 8 dgnd 49 gpio1/irq 41 adcdat2 33 bclk2 31 lrck2 30 cpvref 17 cpp2 25 cpn2 26 cpvpp 20 micvdd 15 spkgnd 46 in1n_sleeve 12 mic_cap 14 jd1 16 in2n 5 spo_rn 44 spkvddr 43 cpgnd 24 dbvdd bclk1 i2c interface in1p_ring2 by-pass capcity near the power pins avdd spkvdd jd1_1 3.0v ~ 3.6v c19 0.1uf/6.3v c20 4.7uf/6.3v sdat mclk c43 0.1uf/6.3v c44 2.2uf/6.3v micvdd r15 0/5% r17 0/5% c41 2.2uf/6.3v c52 22pf/6.3v/nc r8 0/5% lrck2 lrck2 bclk2 bclk2 i2s2 interface c39 22pf/6.3v/nc dcvdd c40 22pf/6.3v/nc dacdat2 adcdat2 dacdat2 r18 0/5% c54 22pf/6.3v/nc c42 2.2uf/6.3v adcdat2 cpvdd micbias1 in1n_sleeve hpol c18 4.7uf/6.3v in2n dacdat1 c30 2.2uf/6.3v c32 4.7uf/6.3v hpor r10 0/5% in2p lrck1 r121 0/5%/1206 size adcdat1 adcdat2 dbvdd c46 10uf/6.3v dacdat2 c25 4.7uf/6.3v 1.71v ~ 3.3v c50 22pf/6.3v/nc dacref lrck2 close to hp jack's gnd r7 0/5% lrck1 lrck1 bclk1 bclk1 i2s1 interface bclk2 mclk c33 22pf/6.3v/nc dgnd avdd c34 22pf/6.3v/nc vref r27 10k/5% agnd power adcdat1 r16 0/5% micbias2 c31 10uf/16v c36 0.1uf/16v spkvdd 3.3v ~ 5.0v dacdat1 sclk dacref r29 100k/5% c49 4.7uf/6.3v micvdd jd1_2 dacdat1 c10 2.2uf/6.3v dbvdd dcvdd micvdd r11 0/5% r9 0/5% mclk c45 22pf/6.3v/nc spo_lp c7 4.7uf/6.3v loutr c51 22pf/6.3v/nc 1.71v ~ 1.9v spo_ln scl_host cpvpp dmic_scl c35 0.1uf/6.3v adcdat1 spo_rp sda_host
alc5672 datasheet 161 rev. 0.75 n p loud spkl 1 2 loud spkr 1 2 c37 680pf/16v c38 680pf/16v spo_ln spo_lp c47 680pf/16v c53 680pf/16v spo_rp spo_rn speaker - stereo mode r24 2.2k/5% cn1 singa_2sj3080-000111f 1 7 6 5 2 4 3 close to codec chip n p c5 1uf/6.3v in2p micbias2 r4 2.2k/5% single-end amic in mic2 2 1 in2p/in2n option 1: line input jd1_1 jd1_2 rj5 100k/5% in2p c27 2.2uf/6.3v c28 2.2uf/6.3v in1p_ring2/in1n_sleeve/hpol/hpor trace width need to >= 40mil line input in2n ph9 1 2 3 4 5 r25 2.2k/5% micbias1 micbias2 in2p/in2n option 2: analog microphone input (differential or single-end) r103 200k/5% in1n_sleeve dbvdd=1.8v dmic_scl dmic_scl dbvdd=1.8v in2p mic11 con2 c d p g dmic1_r input in2p dmic1_l input mic12 con2 c d p g in2p/in2n option 3: 4-ch digital microphone input c4 1uf/6.3v in2p c8 1uf/6.3v in2n r6 2.2k/5% micbias2 r3 2.2k/5% differential amic in mic1 2 1 c68 100pf/6.3v in1p_ring2 in1n_sleeve sw1 up sw2 center in1p_ring2 sw3 down r105 220/5% headset device push button detection circuit r106 20/5% r107 620/5% dmic_scl dbvdd=1.8v dbvdd=1.8v in2n dmic_scl mic13 con2 c d p g in2n dmic2_l input dmic2_r input mic14 con2 c d p g loutr c24 1uf/6.3v c26 1uf/6.3v line out j38 con2 1 2 combo jack function r20 33/5% r21 33/5% hpol hpor r101 22/5% loutl r100 22/5% figure 37. application circuit
alc5672 datasheet 162 rev. 0.75 13. package information 13.1. mechanical dimensions plastic quad flat no-lead package 48 leads 6x6mm 2 outline symbol dimension in mm dimension in inch min nom max min nom max a 0.75 0.85 1.00 0.030 0.034 0.039 a 1 0.00 0.02 0.05 0.000 0.001 0.002 a 3 0.20 ref 0.008 ref b 0.15 0.20 0.25 0.006 0.008 0.010 d/e 6.00bsc 0.236bsc d2/e2 4.15 4.4 4.65 0.163 0.173 0.183 e 0.40bsc 0.016bsc l 0.30 0.40 0.50 0.012 0.016 0.020 notes 1. controlling dimension millimeter(mm). 2. reference documentl jedec mo- 220. figure 38. pa ckage dimension
alc5672 datasheet 163 rev. 0.75 13.2. package thermal information table 20 8. thermal information parameter symbol min typ max units qfn48 (6x6) thermal impedance (junction to case) ? jc - 8.4 - o c/w qfn48 (6x6) thermal impedance (junction to ambient) ? ja - 28 - o c/w *follow jedec pcb: 1. pcb dimension (l x w): 114.3mm x 101.6mm 2. pcb thickness: 1.6mm 3. number of cu layer-pcb: 4-layers (2s2p) 4. pcb via number: 10 5. air flow: 0 (m/s)
alc5672 datasheet 164 rev. 0.75 14. ordering information table 20 9. ordering information part number package status alc5672- cg 48 - pin qfn (6mm x 6mm) in green package (tray) sample alc5672-cgt 48 - pin qfn (6mm x 6mm) in green package (tape & reel) sample alc5672r- cg 48 - pin qfn (6mm x 6mm) in green package (tray) sample ALC5672R-CGt 48 -pin qfn (6mm x 6mm) in green package (tape & reel) sample * r is special for certain assign project purpose, not for general purpose. realtek semiconductor corp. headquarters no. 2, innovation road ii hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com

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